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mb9b 5 10r series 32 - bit arm ? cortex ? - m 3 fm3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 08541 rev.*c revised march 21, 2017 the mb9b 5 10r series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with high - performance and competitive cost. these series are based on the arm cortex - m3 processor with on - chip flash memory and sram, and has peripheral functions s uch as motor control timers, adcs and communication interfaces (usb, can, uart, csio, i 2 c, lin). the products which are described in this data sheet are placed into type4 product categories in fm3 family peripheral manual. features 32 - bit arm cortex - m3 core ? processor version: r2p1 ? up to 144 mhz frequency operation ? memory protection unit (mpu): improves the reliability of an embedded system ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [ flash memory ] these series are based on two independent on - chip flash memories. ? mainfla sh ? up to 512 kbyte ? built - in flash accelerator system with 16 kbyte trace buffer memory ? the read access to flash memory can be achieved without wait cycle up to operation frequency of 72 mhz. even at the operation frequency more than 72 mhz, an equivalent a ccess to flash memory can be obtained by flash accelerator system. ? security function for code protection ? workflash ? 32 kbyte ? read cycle ? 4wait - cycle: the operation frequency more than 72 mhz ? 2wait - cycle: the operation frequency more than 40 mhz, and to 72 mhz ? 0wait - cycle: the operation frequency to 40 mhz ? security function is shared with code protection [ sram ] this series contain a total of up to 64 kbyte on - chip sram. this is composed of two independent sram (sram0, sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 32 kbyte ? sram1: up to 32 kbyte external bus interface ? supports sram, nor and nand flash device ? up to 8 chip selects ? 8 - /16 - bit data width ? up to 25 - bit address bit ? maximum area size: up to 256 mbytes ? supports address/data multiplex ? supports external rdy input usb interface usb interface is composed of device and host. pll for usb is built - in, usb clock can be generated by multiplication of main clock. ? usb device ? usb2.0 full - speed supported ? max 6 endpoint supported ? endpoint 0 is control transfer ? endpoint 1, 2 can be selected bulk - transfer, interrupt - transfer or isochronous - transfer ? endpoint 3 to 5 can be selecte d bulk - transfer or interrupt - transfer ? endpoint 1 to 5 is comprised double buffer ? the size of each endpoint is as follows. ? endpoint 0, 2 to 5: 64 bytes ? endpoint 1: 256 bytes ? usb host ? usb2.0 full/low - speed supported ? bulk - transfer, interrupt - transfer and isoc hronous - transfer support ? usb device connected/dis - connected automatically detect ? in/out token handshake packet automatically ? max 256 - byte packet - length supported ? wake - up function supported can interface (max two channels) ? compatible with can specification 2.0a/b ? maximum transfer rate : 1 mbps ? built - in 32 message buffer
document number: 002 - 08541 rev.*c page 2 of 117 mb9b510r s eries multi - function serial interface (max eight channels) ? 4 channels with 16 steps9 - bit fifo (ch.4 to ch.7), 4 channels without fifo (ch.0 to ch.3) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c ? uart ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control : automatically control the tra nsmission by cts/rts (only ch.4) ? various error detect functions available (parity errors, framing errors, and overrun errors) ? csio ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detect function available ? lin ? lin protocol rev .2.1 supported ? full - duplex double buffer ? master/slave mode supported ? lin break field generate (can be changed 13 to 16 - bit length) ? lin break delimiter generate (can be changed 1 to 4 - bit length) ? various error detect functions available (parity errors, framing errors, and overrun errors) ? i 2 c ? standard - mode (max 100 kbps) / fast - mode (max 400 kbps) supported dma controller (eight channels) dma controller has an independent bus for cpu, so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 - bit (4 gbyte) ? transfer mode: block transfer/burst transfer/demand transfer ? transfer data type: byte/half - word/word ? trans fer block count: 1 to 16 ? number of transfers: 1 to 65536 a/d converter (max 16 channels) ? 12 - bit a/d converter ? successive approximation register type ? built - in 3 unit ? conversion time: 1.0 s @ 5 v ? priority conversion available (priority at 2 levels) ? scanning conversion mode ? built - in fifo for conversion data storage (for scan conversion: 16 steps, for priority conversion: 4 steps) base timer (max eight channels) operation mode is selectable from the followings for each channel. ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer general purpose i/o port this series can use its pins as general purpose i/o ports when they are not used for external bus or peripherals. moreover, the port relocate function is built in. it can set which i/o port the peripheral function can be allocated. ? capable of pull - up control per pin ? capable of reading pin level directly ? built - in the port relocate function ? up 103 fast general purpose i/o ports @ 120 pin package ? some pin is 5 v tolerant i/o. see " 4 list of pin functions " to confirm the corresponding pins. multi - function timer (max three units) the multi - function timer is composed of the following blocks. ? 16 - bit free - run timer 3 ch./unit ? input capture 4 ch./unit ? output compare 6 ch./unit ? a/d activating compare 3 ch./unit ? waveform generator 3 ch./unit ? 16 - bit ppg timer 3 ch./unit the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function
document number: 002 - 08541 rev.*c page 3 of 117 mb9b510r s eries real - time clock (rtc) the real - time clock can count year/month/day/hour/minute/second/a day of the week from 0 0 to 99. ? interru pt function with specifying date and time (year/month/day/hour/minute) is available. this function is also available by specifying only year, month, day, hour or minute. ? timer interrupt function after set time or each set time. ? capable of rewriting the tim e with continuing the time count. ? leap year automatic count is available . quadrature position/revolution counter (qprc) (max three channels) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreove r, it is possible to use up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the followings for each channel. ? free - running ? periodic (=reload) ? one - shot watch counter the watch counter is used for wake up from power consumption mode. ? interval timer: up to 64 s (max) @ sub clock: 32.768 khz external interrupt controller unit ? up to 16 external interrupt input pin ? include one non - maskable interrupt (nmi) watchdog timer (two channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs, a "hardware" watchdog and a "software" watchdog. "hardware" watchdog timer is clocked by low - speed internal cr oscillator. therefore, "hardware" watchdog is active in any p ower consumption mode except stop mode. crc (cyclic redundancy check) accelerator the crc accelerator helps a verify data transmission or storage integrity. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 clock and reset ? clocks five clock sources (2 external oscillators, 2 internal cr oscillator, and main pll) that are dynamically selectable. ? main clock: 4 mhz to 48 mhz ? sub clock: 32.768 khz ? hig h - speed internal cr clock: 4 mhz ? low - speed internal cr clock: 100 khz ? resets ? reset requests from initx pin ? power on reset ? software reset ? watchdog timers reset ? low - voltage detector reset ? clock supervisor reset clock super visor (csv) clocks generated by internal cr oscillators are used to supervise abnormality of the external clocks. ? external osc clock failure (clock stop) is detected, reset is asserted. ? external osc frequency anomaly is detected, interrupt or reset is asserted. low - voltage detector (lvd) this series include 2 - stage monitoring of voltage on the vcc pins. when the voltage falls below the voltage has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation
document number: 002 - 08541 rev.*c page 4 of 117 mb9b510r s eries low - power c onsumption mode three power consumption modes supported. ? sleep ? timer ? stop debug ? serial wire jtag debug port (swj - dp) ? embedded trace macrocells (etm) provide comprehensive debug and trace facilities. power supply two power supplies ? wide range voltage: vcc = 2.7 v to 5.5 v ? usb for usb i/o voltage: usbvcc = 3.0 v to 3.6 v (when usb is used) = 2.7 v to 5.5 v (when gpio is used)
document number: 002 - 08541 rev.*c page 5 of 117 mb9b510r s eries table of contents features ................................ ................................ ................................ ................................ ................................ .............. 1 1. product lineup ................................ ................................ ................................ ................................ ............................ 7 2. packages ................................ ................................ ................................ ................................ ................................ ...... 9 3. pin assignments ................................ ................................ ................................ ................................ ....................... 10 4. list of pin functions ................................ ................................ ................................ ................................ ................. 14 5. i/o circuit type ................................ ................................ ................................ ................................ .......................... 41 6. handling precautions ................................ ................................ ................................ ................................ ................ 46 6.1 precautions for product design ................................ ................................ ................................ ................................ 46 6.2 precautions for package mounting ................................ ................................ ................................ ........................... 47 6.3 precautions for use environment ................................ ................................ ................................ ............................. 49 7. handling devices ................................ ................................ ................................ ................................ ....................... 50 8. block diagram ................................ ................................ ................................ ................................ ........................... 52 9. memory size ................................ ................................ ................................ ................................ .............................. 52 10. memory map ................................ ................................ ................................ ................................ .............................. 53 11. pin status in each cpu state ................................ ................................ ................................ ................................ ... 57 12. electrical characteristics ................................ ................................ ................................ ................................ .......... 61 12.1 absolute maximum ratings ................................ ................................ ................................ ................................ ...... 61 12.2 recommended operating conditions ................................ ................................ ................................ ....................... 63 12.3 dc characteristics ................................ ................................ ................................ ................................ .................... 64 12.3 .1 current rating ................................ ................................ ................................ ................................ ....................... 64 12.3.2 pin characteristics ................................ ................................ ................................ ................................ ................. 66 12.4 ac characteristics ................................ ................................ ................................ ................................ .................... 68 12.4.1 main clock input characteristics ................................ ................................ ................................ ........................... 68 12.4.2 sub clock input characteristics ................................ ................................ ................................ ............................. 69 12.4.3 internal cr oscillation characteristics ................................ ................................ ................................ ................... 69 12.4.4 operating conditions of main an d usb pll (in the case of using main clock for input of pll) ............................ 70 12.4.5 operating conditions of main pll (in the case of using high - speed internal cr) ................................ ................. 70 12.4.6 reset input characteristics ................................ ................................ ................................ ................................ .... 71 12.4.7 power - on reset timing ................................ ................................ ................................ ................................ ......... 71 12.4.8 external bus timing ................................ ................................ ................................ ................................ ............... 72 12.4.9 base timer input timing ................................ ................................ ................................ ................................ ........ 81 12.4.10 csio/uart timing ................................ ................................ ................................ ................................ ................ 82 12.4.11 external input timing ................................ ................................ ................................ ................................ ............. 90 12.4.12 quadrature position/revolution counter timing ................................ ................................ ................................ ..... 91 12.4.13 i 2 c timing ................................ ................................ ................................ ................................ .............................. 93 12.4.14 etm timing ................................ ................................ ................................ ................................ ........................... 94 12.4.15 jtag timing ................................ ................................ ................................ ................................ .......................... 95 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ ................. 96 12.6 usb characteristics ................................ ................................ ................................ ................................ .................. 99 12.7 low - voltage detec tion characteristics ................................ ................................ ................................ ................... 103 12.7.1 low - voltage detection reset ................................ ................................ ................................ .............................. 103 12.7.2 interrupt of low - voltage detection ................................ ................................ ................................ ...................... 103 12.8 mainflash memory write/erase characteristics ................................ ................................ ................................ ..... 104 12.8.1 write / erase time ................................ ................................ ................................ ................................ ................ 104 12.8.2 erase/write cycles and data hold time ................................ ................................ ................................ .................. 104 12.9 workflash memory write/erase characteristics ................................ ................................ ................................ .... 104 12.9.1 write / erase time ................................ ................................ ................................ ................................ ................ 104
document number: 002 - 08541 rev.*c page 6 of 117 mb9b510r s eries 12 .9.2 erase/write cycles and data hold time ................................ ................................ ................................ .................. 104 12.10 return time from low - power consumption mode ................................ ................................ ................................ . 105 12.10.1 return factor: interrupt ................................ ................................ ................................ ................................ ........ 105 12.10.2 return factor: reset ................................ ................................ ................................ ................................ ............ 107 13. ordering information ................................ ................................ ................................ ................................ ............... 109 14. package dimensions ................................ ................................ ................................ ................................ ............... 110 15. major changes ................................ ................................ ................................ ................................ ......................... 114 document h istory ................................ ................................ ................................ ................................ ............................... 116 sales, solutions, and legal information ................................ ................................ ................................ ........................... 117
document number: 002 - 08541 rev.*c page 7 of 117 mb9b510r s eries 1. product lineup memory size product name mb9bf 5 12n/r mb9bf 5 14n/r mb9bf 5 15n/r mb9bf 5 16r mainflash 128 kbyte 256 kbyte 384 kbyte 512 kbyte workflash 32 kbyte 32 kbyte 32 kbyte 32 kbyte on - chip ram 16 kbyte 32 kbyte 48 kbyte 64 kbyte sram0 8 kbyte 16 kbyte 24 kbyte 32 kbyte sram1 8 kbyte 16 kbyte 24 kbyte 32 kbyte function product name mb9bf 5 12n mb9bf 5 14n mb9bf 5 15n mb9bf 5 16n mb9bf 5 12r mb9bf 5 14r mb9bf 5 15r mb9bf 5 16r pin count 1 00 /112 1 20 cpu cortex - m3 freq. 144 mhz power supply voltage range vcc : 2.7 v to 5.5 v (usbvcc : 3.0 v to 3.6 v) usb2.0 ( device /host) 1 ch . can 2 ch. (max) dmac 8 ch . external bus interface addr: 25 - bit (max) r/wdata: 8 - /16 - bit (max) cs: 8 (max) support: sram, nor flash addr: 25 - bit (max) r/wdata: 8 - /16 - bit (max) cs: 8 (max) support: sram, nor & nand flash mf serial interface (uart/csio/lin/i 2 c) 8 ch . (max) ch.4 to ch.7: fifo (16steps 9 - bit) ch.0 to ch.3: no fifo base timer (pwc/reload timer/pwm/ppg) 8 ch . (max) mf - timer a/d activation compare 3 ch. 3 units (max) input capture 4 ch. free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 3 ch . (max) dual timer 1 unit real - time clock 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 16 pins (max) + nmi 1 i/o ports 83 pins (max) 103 pins (max) 12 - bit a/d converter 16 ch. (3 units)
document number: 002 - 08541 rev.*c page 8 of 117 mb9b510r s eries product name mb9bf 5 12n mb9bf 5 14n mb9bf 5 15n mb9bf 5 16n mb9bf 5 12r mb9bf 5 14r mb9bf 5 15r mb9bf 5 16r csv (clock super visor) yes lvd (low - voltage detector) 2 ch. internal osc high - speed 4 mhz low - speed 100 khz debug function swj - dp/etm note : ? all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the general i/o port according to your function use. see " 12 electrical characteristics 12.4 ac characteristics 12.4.3 i nternal cr oscillation characteristics " for accuracy of built - in cr.
document number: 002 - 08541 rev.*c page 9 of 117 mb9b510r s eries 2. packages product name package mb9bf 5 12n mb9bf 5 14n mb9bf 5 15n mb9bf 5 16n mb9bf 5 12r mb9bf 5 14r mb9bf 5 15r mb9bf 5 16r qfp : pqh100 (0. 6 5 mm pitch) ? - lqfp : lqi100 (0.5 mm pitch) ? - lqfp: lqm120 (0.5 mm pitch) - ? fbga : lbc112 (0.8 mm pitch) ? - ? : supported note : ? see " 14 . package dimensions " for detailed information on each package.
document number: 002 - 08541 rev.*c page 10 of 117 mb9b510r s eries 3. pin assignment s lqi100 note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (e pfr) to select the pin. ( top view ) vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1/mrdy_0 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3/tx0_2/moex_0 p63/int03_0/sin5_1/rx0_2/mwex_0 p0f/nmix/crout_1/rtcco_0/dtti2x_0/dtti2x_1/subout_0 p0e/cts4_0/tiob3_2/ic13_0/ic23_0/rto25_1/mdqm1_0 p0d/rts4_0/tioa3_2/ic12_0/ic22_0/rto24_1/mdqm0_0 p0c/sck4_0/tioa6_1/ic11_0/ic21_0/rto23_1/male_0 p0b/sot4_0/tiob6_1/ic10_0/ic20_0/rto22_1/mcsx0_0 p0a/sin4_0/int00_2/frck1_0/frck2_0/rto21_1/mcsx1_0 p09/traceclk/tiob0_2/rts4_2/rto20_1/mcsx2_0 p08/traced3/tioa0_2/cts4_2/zin2_1/mcsx3_0 p07/traced2/adtg_0/sck4_2/bin2_1/mclkout_0 p06/traced1/tiob5_2/sot4_2/int01_1/ain2_1/mcsx4_0 p05/traced0/tioa5_2/sin4_2/int00_1/mcsx5_0 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_0 p01/tck/swclk p00/trstx/mcsx7_0 vcc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vcc 1 75 vss p50/int00_0/ain0_2/sin3_1/rto10_0/madata00_0 2 74 p20/int05_0/crout_0/ain1_1/mad24_0 p51/int01_0/bin0_2/sot3_1/rto11_0/madata01_0 3 73 p21/sin0_0/int06_1/bin1_1 p52/int02_0/zin0_2/sck3_1/rto12_0/madata02_0 4 72 p22/sot0_0/tiob7_1/zin1_1 p53/sin6_0/tioa1_2/int07_2/rto13_0/madata03_0 5 71 p23/sck0_0/tioa7_1 p54/sot6_0/tiob1_2/rto14_0/madata04_0 6 70 p1f/an15/adtg_5/frck0_1/mad23_0 p55/sck6_0/adtg_1/rto15_0/madata05_0 7 69 p1e/an14/rts4_1/dtti0x_1/mad22_0 p56/int08_2/dtti1x_0/madata06_0 8 68 p1d/an13/cts4_1/ic03_1/mad21_0 p30/ain0_0/tiob0_1/int03_2/madata07_0 9 67 p1c/an12/sck4_1/ic02_1/mad20_0 p31/bin0_0/tiob1_1/sck6_1/int04_2/madata08_0 10 66 p1b/an11/sot4_1/ic01_1/mad19_0 p32/zin0_0/tiob2_1/sot6_1/int05_2/madata09_0 11 65 p1a/an10/sin4_1/int05_1/ic00_1/mad18_0 p33/int04_0/tiob3_1/sin6_1/adtg_6/madata10_0 12 64 p19/an09/sck2_2/mad17_0 p34/frck0_0/tiob4_1/tx0_1/madata11_0 13 63 p18/an08/sot2_2/mad16_0 p35/ic03_0/tiob5_1/rx0_1/int08_1/madata12_0 14 62 avss p36/ic02_0/sin5_2/int09_1/madata13_0 15 61 avrh p37/ic01_0/sot5_2/int10_1/madata14_0 16 60 avcc p38/ic00_0/sck5_2/int11_1/madata15_0 17 59 p17/an07/sin2_2/int04_1/mad15_0 p39/dtti0x_0/adtg_2 18 58 p16/an06/sck0_1/mad14_0 p3a/rto00_0/tioa0_1/rtcco_2/subout_2 19 57 p15/an05/sot0_1/ic03_2/mad13_0 p3b/rto01_0/tioa1_1 20 56 p14/an04/sin0_1/int03_1/ic02_2/mad12_0 p3c/rto02_0/tioa2_1 21 55 p13/an03/sck1_1/rtcco_1/subout_1/ic01_2/mad11_0 p3d/rto03_0/tioa3_1 22 54 p12/an02/sot1_1/tx1_2/ic00_2/mad10_0 p3e/rto04_0/tioa4_1 23 53 p11/an01/sin1_1/int02_1/rx1_2/frck0_2/mad09_0 p3f/rto05_0/tioa5_1 24 52 p10/an00 vss 25 51 vcc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1 p43/tioa3_0/rto13_1/adtg_7 p44/tioa4_0/rto14_1/mad00_0 p45/tioa5_0/rto15_1/mad01_0 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2/mad02_0 p49/tiob0_0/ic10_1/ain0_1/sot3_2/mad03_0 p4a/tiob1_0/ic11_1/bin0_1/sck3_2/mad04_0 p4b/tiob2_0/ic12_1/zin0_1/mad05_0 p4c/tiob3_0/ic13_1/sck7_1/ain1_2/mad06_0 p4d/tiob4_0/frck1_1/sot7_1/bin1_2/mad07_0 p4e/tiob5_0/int06_2/sin7_1/zin1_2/mad08_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 100
document number: 002 - 08541 rev.*c page 11 of 117 mb9b510r s eries lqm120 note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (e pfr) to select the pin. ( top view) vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1/mrdy_0 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3/tx0_2/moex_0 p63/int03_0/sin5_1/rx0_2/rto20_0/mwex_0 p64/tioa7_0/sot5_1/int10_2/frck2_1/rto21_0 p65/tiob7_0/sck5_1/ic23_1/rto22_0 p66/sin3_0/adtg_8/int11_2/ic22_1/rto23_0 p67/sot3_0/tioa7_2/ic21_1/rto24_0 p68/sck3_0/tiob7_2/int12_2/ic20_1/rto25_0 p0f/nmix/crout_1/rtcco_0/dtti2x_0/dtti2x_1/subout_0 p0e/cts4_0/tiob3_2/ic13_0/ic23_0/rto25_1/mdqm1_0 p0d/rts4_0/tioa3_2/ic12_0/ic22_0/rto24_1/mdqm0_0 p0c/sck4_0/tioa6_1/ic11_0/ic21_0/rto23_1/male_0 p0b/sot4_0/tiob6_1/ic10_0/ic20_0/rto22_1/mcsx0_0 p0a/sin4_0/int00_2/frck1_0/frck2_0/rto21_1/mcsx1_0 p09/traceclk/tiob0_2/rts4_2/rto20_1/mcsx2_0 p08/traced3/tioa0_2/cts4_2/zin2_1/mcsx3_0 p07/traced2/adtg_0/sck4_2/bin2_1/mclkout_0 p06/traced1/tiob5_2/sot4_2/int01_1/ain2_1/mcsx4_0 p05/traced0/tioa5_2/sin4_2/int00_1/mcsx5_0 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_0 p01/tck/swclk p00/trstx/mcsx7_0 vcc 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 vcc 1 90 vss p50/int00_0/ain0_2/sin3_1/rto10_0/madata00_0 2 89 p20/int05_0/crout_0/ain1_1/mad24_0 p51/int01_0/bin0_2/sot3_1/rto11_0/madata01_0 3 88 p21/sin0_0/int06_1/bin1_1 p52/int02_0/zin0_2/sck3_1/rto12_0/madata02_0 4 87 p22/sot0_0/tiob7_1/zin1_1 p53/sin6_0/tioa1_2/int07_2/rto13_0/madata03_0 5 86 p23/sck0_0/tioa7_1/rto00_1 p54/sot6_0/tiob1_2/rto14_0/madata04_0 6 85 p24/rx1_0/sin2_1/int01_2/rto01_1 p55/sck6_0/adtg_1/rto15_0/madata05_0 7 84 p25/tx1_0/sot2_1/rto02_1 p56/sin1_0/int08_2/dtti1x_0/madata06_0 8 83 p26/sck2_1/rto03_1 p57/sot1_0/madata07_0 9 82 p27/tioa6_2/int02_2/rto04_1 p58/sck1_0/ain2_0/madata08_0 10 81 p28/tiob6_2/adtg_4/rto05_1 p59/sin7_0/rx1_1/int09_2/bin2_0/madata09_0 11 80 p1f/an15/adtg_5/frck0_1/mad23_0 p5a/sot7_0/tx1_1/zin2_0/madata10_0 12 79 p1e/an14/rts4_1/dtti0x_1/mad22_0 p5b/sck7_0/madata11_0 13 78 p1d/an13/cts4_1/ic03_1/mad21_0 p30/ain0_0/tiob0_1/int03_2/madata12_0 14 77 p1c/an12/sck4_1/ic02_1/mad20_0 p31/bin0_0/tiob1_1/sck6_1/int04_2/madata13_0 15 76 p1b/an11/sot4_1/ic01_1/mad19_0 p32/zin0_0/tiob2_1/sot6_1/int05_2/madata14_0 16 75 p1a/an10/sin4_1/int05_1/ic00_1/mad18_0 p33/int04_0/tiob3_1/sin6_1/adtg_6/madata15_0 17 74 p19/an09/sck2_2/mad17_0 p34/frck0_0/tiob4_1/tx0_1/mnale_0 18 73 p18/an08/sot2_2/mad16_0 p35/ic03_0/tiob5_1/rx0_1/int08_1/mncle_0 19 72 avss p36/ic02_0/sin5_2/int09_1/mnwex_0 20 71 avrh p37/ic01_0/sot5_2/int10_1/mnrex_0 21 70 avcc p38/ic00_0/sck5_2/int11_1 22 69 p17/an07/sin2_2/int04_1/mad15_0 p39/dtti0x_0/adtg_2 23 68 p16/an06/sck0_1/mad14_0 p3a/rto00_0/tioa0_1/rtcco_2/subout_2 24 67 p15/an05/sot0_1/ic03_2/mad13_0 p3b/rto01_0/tioa1_1 25 66 p14/an04/sin0_1/int03_1/ic02_2/mad12_0 p3c/rto02_0/tioa2_1 26 65 p13/an03/sck1_1/rtcco_1/subout_1/ic01_2/mad11_0 p3d/rto03_0/tioa3_1 27 64 p12/an02/sot1_1/tx1_2/ic00_2/mad10_0 p3e/rto04_0/tioa4_1 28 63 p11/an01/sin1_1/int02_1/rx1_2/frck0_2/mad09_0 p3f/rto05_0/tioa5_1 29 62 p10/an00 vss 30 61 vcc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1 p43/tioa3_0/rto13_1/adtg_7 p44/tioa4_0/rto14_1/mad00_0 p45/tioa5_0/rto15_1/mad01_0 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2/mad02_0 p49/tiob0_0/ic10_1/ain0_1/sot3_2/mad03_0 p4a/tiob1_0/ic11_1/bin0_1/sck3_2/mad04_0 p4b/tiob2_0/ic12_1/zin0_1/mad05_0 p4c/tiob3_0/ic13_1/sck7_1/ain1_2/mad06_0 p4d/tiob4_0/frck1_1/sot7_1/bin1_2/mad07_0 p4e/tiob5_0/int06_2/sin7_1/zin1_2/mad08_0 p70/tx0_0/tioa4_2 p71/rx0_0/int13_2/tiob4_2 p72/sin2_0/int14_2/tioa6_0 p73/sot2_0/int15_2/tiob6_0 p74/sck2_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 120
document number: 002 - 08541 rev.*c page 12 of 117 mb9b510r s eries pqh100 note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (e pfr ) to select the pin. ( top view) p50/int00_0/ain0_2/sin3_1/rto10_0/madata00_0 vcc vss p81/udp0 p80/udm0 usbvcc p60/sin5_0/tioa2_2/int15_1/mrdy_0 p61/sot5_0/tiob2_2/uhconx p62/sck5_0/adtg_3/tx0_2/moex_0 p63/int03_0/sin5_1/rx0_2/mwex_0 p0f/nmix/crout_1/rtcco_0/dtti2x_0/dtti2x_1/subout_0 p0e/cts4_0/tiob3_2/ic13_0/ic23_0/rto25_1/mdqm1_0 p0d/rts4_0/tioa3_2/ic12_0/ic22_0/rto24_1/mdqm0_0 p0c/sck4_0/tioa6_1/ic11_0/ic21_0/rto23_1/male_0 p0b/sot4_0/tiob6_1/ic10_0/ic20_0/rto22_1/mcsx0_0 p0a/sin4_0/int00_2/frck1_0/frck2_0/rto21_1/mcsx1_0 p09/traceclk/tiob0_2/rts4_2/rto20_1/mcsx2_0 p08/traced3/tioa0_2/cts4_2/zin2_1/mcsx3_0 p07/traced2/adtg_0/sck4_2/bin2_1/mclkout_0 p06/traced1/tiob5_2/sot4_2/int01_1/ain2_1/mcsx4_0 p05/traced0/tioa5_2/sin4_2/int00_1/mcsx5_0 p04/tdo/swo p03/tms/swdio p02/tdi/mcsx6_0 p01/tck/swclk p00/trstx/mcsx7_0 vcc vss p20/int05_0/crout_0/ain1_1/mad24_0 p21/sin0_0/int06_1/bin1_1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p51/int01_0/bin0_2/sot3_1/rto11_0/madata01_0 81 50 p22/sot0_0/tiob7_1/zin1_1 p52/int02_0/zin0_2/sck3_1/rto12_0/madata02_0 82 49 p23/sck0_0/tioa7_1 p53/sin6_0/tioa1_2/int07_2/rto13_0/madata03_0 83 48 p1f/an15/adtg_5/frck0_1/mad23_0 p54/sot6_0/tiob1_2/rto14_0/madata04_0 84 47 p1e/an14/rts4_1/dtti0x_1/mad22_0 p55/sck6_0/adtg_1/rto15_0/madata05_0 85 46 p1d/an13/cts4_1/ic03_1/mad21_0 p56/int08_2/dtti1x_0/madata06_0 86 45 p1c/an12/sck4_1/ic02_1/mad20_0 p30/ain0_0/tiob0_1/int03_2/madata07_0 87 44 p1b/an11/sot4_1/ic01_1/mad19_0 p31/bin0_0/tiob1_1/sck6_1/int04_2/madata08_0 88 43 p1a/an10/sin4_1/int05_1/ic00_1/mad18_0 p32/zin0_0/tiob2_1/sot6_1/int05_2/madata09_0 89 42 p19/an09/sck2_2/mad17_0 p33/int04_0/tiob3_1/sin6_1/adtg_6/madata10_0 90 41 p18/an08/sot2_2/mad16_0 p34/frck0_0/tiob4_1/tx0_1/madata11_0 91 40 avss p35/ic03_0/tiob5_1/rx0_1/int08_1/madata12_0 92 39 avrh p36/ic02_0/sin5_2/int09_1/madata13_0 93 38 avcc p37/ic01_0/sot5_2/int10_1/madata14_0 94 37 p17/an07/sin2_2/int04_1/mad15_0 p38/ic00_0/sck5_2/int11_1/madata15_0 95 36 p16/an06/sck0_1/mad14_0 p39/dtti0x_0/adtg_2 96 35 p15/an05/sot0_1/ic03_2/mad13_0 p3a/rto00_0/tioa0_1/rtcco_2/subout_2 97 34 p14/an04/sin0_1/int03_1/ic02_2/mad12_0 p3b/rto01_0/tioa1_1 98 33 p13/an03/sck1_1/rtcco_1/subout_1/ic01_2/mad11_0 p3c/rto02_0/tioa2_1 99 32 p12/an02/sot1_1/tx1_2/ic00_2/mad10_0 p3d/rto03_0/tioa3_1 100 31 p11/an01/sin1_1/int02_1/rx1_2/frck0_2/mad09_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p3e/rto04_0/tioa4_1 p3f/rto05_0/tioa5_1 vss vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1 p43/tioa3_0/rto13_1/adtg_7 p44/tioa4_0/rto14_1/mad00_0 p45/tioa5_0/rto15_1/mad01_0 c vss vcc p46/x0a p47/x1a initx p48/dtti1x_1/int14_1/sin3_2/mad02_0 p49/tiob0_0/ic10_1/ain0_1/sot3_2/mad03_0 p4a/tiob1_0/ic11_1/bin0_1/sck3_2/mad04_0 p4b/tiob2_0/ic12_1/zin0_1/mad05_0 p4c/tiob3_0/ic13_1/sck7_1/ain1_2/mad06_0 p4d/tiob4_0/frck1_1/sot7_1/bin1_2/mad07_0 p4e/tiob5_0/int06_2/sin7_1/zin1_2/mad08_0 pe0/md1 md0 pe2/x0 pe3/x1 vss vcc p10/an00 qfp - 100
document number: 002 - 08541 rev.*c page 13 of 117 mb9b510r s eries lbc112 note : ? the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. (top view) h j 11 a b c 6 7 k l d e f g 8 9 10 3 4 5 vcc vcc 1 2 vss vcc p50 p53 p3f vss p4e md1 vss x1a initx an01 vss vcc vss p20 p23 an12 an09 an06 an03 vss p40 p30 p34 p37 p3b p35 p44 trstx p4d an02 vss an14 an10 an07 an04 p22 an13 p0b p07 tms/ swdio udp0 udm0 usbvcc p0e vss an08 p52 p61 p0f p0c p08 vss p32 p36 p43 p49 p42 p4c p3a p3d vss p09 p0a p48 p4b p56 p63 index an05 p55 x0 x1 vss vss p33 p39 p38 p3c p3e an00 vcc vss c x0a vss p41 p45 p4a md0 vss p54 vss tdi p21 an15 an11 avrh avss avcc p31 p60 p62 p06 tdo/ swo p05 vss p0d p51 tck/ swclk pfbga - 112
document number: 002 - 08541 rev.*c page 14 of 117 mb9b510r s eries 4. list of pin functions list of pin numbers the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 1 b1 1 79 vcc - 2 c1 2 80 p50 e h int00_0 ain0_2 sin3_1 rto10_0 (ppg10_0) m a data0 0_0 3 c2 3 81 p51 e h int01_0 bin0_2 sot3_1 (sda3_1) rto11_0 (ppg10_0) m a data 0 1 _0 4 b3 4 82 p52 e h int02_0 zin0_2 sck3_1 (scl3_1) rto12_0 (ppg12_0) m a data 0 2 _0 5 d1 5 83 p53 e h sin6_0 tioa1_2 int07_2 rto13_0 (ppg12_0) m a data 0 3 _0 6 d2 6 84 p54 e i sot6_0 (sda6_0) tiob1_2 rto14_0 (ppg14_0) m a data 0 4 _0 7 d3 7 85 p55 e i sck6_0 (scl6_0) adtg_1 rto15_0 (ppg14_0) m a data 0 5 _0
document number: 002 - 08541 rev.*c page 15 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 8 d5 8 86 p56 e h int08_2 dtti1x_0 m adata06_0 - - - sin1_0 ( 120pin only) - - 9 - p57 e i sot1_0 (sda1_0) m adata07_0 - - 10 - p58 e i sck1_0 (scl1_0) ain2_0 m adata08_0 - - 11 - p59 e h sin7_0 rx1_1 int09_2 bin2_0 m adata09_0 - - 12 - p5a e i sot7_0 (sda7_0) tx1_1 zin2_0 m adata10_0 - - 13 - p5b e i sck7_0 (scl7_0) madata11_0 9 e1 14 87 p30 e h ain0_0 tiob0_1 int03_2 - madata07_0 (100pin only) - - 14 - m adata12_0 (120pin only) 10 e2 15 88 p31 e h bin0_0 tiob1_1 sck6_1 (scl6_1) int04_2 - madata08_0 (100pin only) - - 15 - m adata13_0 (120pin only)
document number: 002 - 08541 rev.*c page 16 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 11 e3 16 89 p32 e h zin0_0 tiob2_1 sot6_1 (sda6_1) int05_2 - madata09_0 (100pin only) - - 16 - m adata14_0 (120pin only) 12 e4 17 90 p33 e h int04_0 tiob3_1 sin6_1 adtg_6 - madata10_0 (100pin only) - - 17 - m adata15_0 (120pin only) 13 f1 18 91 p34 e i frck0_0 tiob4_1 tx0_1 - madata11_0 (100pin only) - - 18 - m nale_0 (120pin only) 14 f2 19 92 p35 e h ic03_0 tiob5_1 rx0_1 int08_1 - madata12_0 (100pin only) - - 19 - m ncle_0 (120pin only) 15 f3 20 93 p36 e h ic02_0 sin5_2 int09_1 - madata13_0 (100pin only) - - 20 - m nwex_0 (120pin only) 16 g1 21 94 p37 e h ic01_0 sot5_2 (sda5_2) int10_1 - madata14_0 (100pin only) - - 21 - m nrex_0 (120pin only)
document number: 002 - 08541 rev.*c page 1 7 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 17 g2 22 95 p38 e h ic00_0 sck5_2 (scl5_2) int11_1 - madata15_0 (100pin only) 18 f4 23 96 p39 e i dtti0x_0 adtg_2 19 g3 24 97 p3a g i rto00_0 (ppg00_0) tioa0_1 rtcco_2 subout_2 - b2 - - vss - 20 h1 25 98 p3b g i rto01_0 (ppg00_0) tioa1_1 21 h2 26 99 p3c g i rto02_0 (ppg02_0) tioa2_1 22 g4 27 100 p3d g i rto03_0 (ppg02_0) tioa3_1 23 h3 28 1 p3e g i rto04_0 (ppg04_0) tioa4_1 24 j2 29 2 p3f g i rto05_0 (ppg04_0) tioa5_1 25 l1 30 3 vss - 26 j1 31 4 vcc - 27 j4 32 5 p40 g h tioa0_0 rto10_1 (ppg10_1) int12_1 28 l5 33 6 p41 g h tioa1_0 rto11_1 (ppg10_1) int13_1 29 k5 34 7 p42 g i tioa2_0 rto12_1 (ppg12_1) 30 j5 35 8 p43 g i tioa3_0 rto13_1 (ppg12_1)
document number: 002 - 08541 rev.*c page 18 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 adtg_7 - k2 - - vss - - j3 - - vss - - h4 - - vss - 31 h5 36 9 p44 g i tioa4_0 rto14_1 (ppg14_1) mad 00_0 32 l6 37 10 p45 g i tioa5_0 rto15_1 (ppg14_1) mad 01_0 33 l2 38 11 c - 34 l4 39 12 vss - 35 k1 40 13 vcc - 36 l3 41 14 p46 d m x0a 37 k3 42 15 p47 d n x1a 38 k4 43 16 initx b c 39 k6 44 17 p48 e h dtti1x_1 int14_1 sin3_2 mad 02_0 40 j6 45 18 p49 e i tiob0_0 ic10_1 ain0_1 sot3_2 (sda3_2) mad 03_0 41 l7 46 19 p4a e i tiob1_0 ic11_1 bin0_1 sck3_2 (scl3_2) mad 0 4 _0 42 k7 47 20 p4b e i tiob2_0 ic12_1 zin0_1 mad 05_0 43 h6 48 21 p4c i* i tiob3_0 ic13_1 sck7_1 (scl7_1) ain1_2 mad 06_0
document number: 002 - 08541 rev.*c page 19 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 44 j7 49 22 p4d i* i tiob4_0 frck1_1 sot7_1 (sda7_1) bin1_2 mad 07_0 45 k8 50 23 p4e i* h tiob5_0 int06_2 sin7_1 zin1_2 mad 08_0 - - 51 - p70 e i tx0_0 tioa4_2 - - 52 - p71 e h rx0_0 int13_2 tiob4_2 - - 53 - p72 e h sin2_0 int14_2 tioa6_0 - - 54 - p73 e h sot2_0 (sda2_0) int15_2 tiob6_0 - - 55 - p74 e i sck2_0 (scl2_0) 46 k9 56 24 pe0 c p md1 47 l8 57 25 md0 j d 48 l9 58 26 pe2 a a x0 49 l10 59 27 pe3 a b x1 50 l11 60 28 vss - 51 k11 61 29 vcc - 52 j11 62 30 p10 f k an00 53 j10 63 31 p11 f l an01 sin1_1 int02_1 rx1_2 frck0_2 mad09_0 - k10 - - vss - - j9 - - vss -
document number: 002 - 08541 rev.*c page 20 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 54 j8 64 32 p12 f k an02 sot1_1 (sda1_1) tx1_2 ic00_2 mad 10_0 55 h10 65 33 p13 f k an03 sck1_1 (scl1_1) rtcco_1 subout_1 ic01_2 mad 11_0 56 h9 66 34 p14 f l an04 sin0_1 int03_1 ic02_2 m ad12_0 57 h7 67 35 p15 f k an05 sot0_1 (sda0_1) ic03_2 m ad13_0 58 g10 68 36 p16 f k an06 sck0_1 (scl0_1) m ad14_0 59 g9 69 37 p17 f l an07 sin2_2 int04_1 m ad15_0 60 h11 70 38 avcc - 61 f11 71 39 avrh - 62 g11 72 40 avss - 63 g8 73 41 p18 f k an08 sot2_2 (sda2_2) m ad16_0 64 f10 74 42 p19 f k an09 sck2_2 (scl2_2) m ad17_0 65 f9 75 43 p1a f l an10 sin4_1 int05_1 ic00_1 m ad18_0 - h8 - - vss -
document number: 002 - 08541 rev.*c page 21 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 66 e11 76 44 p1b f k an11 sot4_1 (sda4_1) ic01_1 m ad19_0 67 e10 77 45 p1c f k an12 sck4_1 (scl4_1) ic02_1 m ad20_0 68 f8 78 46 p1d f k an13 cts4_1 ic03_1 m ad21_0 69 e9 79 47 p1e f k an14 rts4_1 dtti0x_1 m ad22_0 70 d11 80 48 p1f f k an15 adtg_5 frck0_1 m ad23_0 - - 8 1 - p28 e i tiob6_2 adtg_4 rto05_1 (ppg04_1) - - 82 - p27 e h tioa6_2 int02_2 rto04_1 (ppg04_1) - - 83 - p26 e i sck2_1 (scl2_1) rto03_1 (ppg02_1) - - 84 - p25 e i tx1_0 sot2_1 (sda2_1) rto02_1 (ppg02_1) - b10 - - vss - - c9 - - vss - - - 85 - p24 e h rx1_0 sin2_1 int01_2 rto01_1 (ppg00_1)
document number: 002 - 08541 rev.*c page 22 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 7 1 d10 8 6 49 p23 e i sck0_0 (scl0_0) tioa7_1 - - - rto00_1 (ppg00_1) 7 2 e8 8 7 50 p22 e i sot0_0 (sda0_0) tiob7_1 zin1_1 7 3 c11 8 8 51 p21 e h sin0_0 int06_1 bin1_1 7 4 c10 8 9 52 p20 e h int05_0 crout _0 ain1_1 mad24_0 75 a11 90 53 vss - 76 a10 91 54 vcc - 77 a9 92 55 p00 e e trstx mcsx7_0 78 b9 93 56 p01 e e tck swclk 79 b11 94 57 p02 e e tdi mcsx6_0 80 a8 95 58 p03 e e tms swdio 81 b8 96 59 p04 e e tdo swo 82 c8 97 60 p05 e f traced0 tioa5_2 sin4_2 int00_1 mcsx5_0 - d8 - - vss - 83 d9 98 61 p06 e f traced1 tiob5_2 sot4_2 (sda4_2) int01_1 ain2_1 mcsx4_0
document number: 002 - 08541 rev.*c page 23 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 84 a7 99 62 p07 e g traced2 adtg_0 sck4_2 (scl4_2) bin2_1 mclkout_0 85 b7 100 63 p08 e g traced3 tioa0_2 cts4_2 zin2_1 mcsx3_0 86 c7 101 64 p09 e g traceclk tiob0_2 rts4_2 rto20_1 (ppg20_1) mcsx2_0 87 d7 102 65 p0a i * h sin4_0 int00_2 frck1_0 frck2_0 rto21_1 (ppg20_1) m csx1_0 88 a6 103 66 p0b i * i sot4_0 (sda4_0) tiob6_1 ic10_0 ic20_0 rto22_1 (ppg22_1) m csx0_0 89 b6 104 67 p0c i * i sck4_0 (scl4_0) tioa6_1 ic11_0 ic21_0 rto23_1 ma le_0 90 c6 105 68 p0d e i rts4_0 tioa3_2 ic12_0 ic22_0 rto24_1 (ppg24_1) m dqm0_0
document number: 002 - 08541 rev.*c page 24 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 91 a5 106 69 p0e e i cts4_0 tiob3_2 ic13_0 ic23_0 rto25_1 (ppg24_1) m dqm1_0 - d4 - - vss - - c3 - - vss - 92 b5 107 70 p0f e j nmix crout_1 rtcco_0 subout_0 dtti2x_0 dtti2x_1 - - 108 - p68 g h sck3_0 (scl3_0) tiob7_2 int12_2 ic20_1 rto25_0 (ppg24_0) - - 109 - p67 g i sot3_0 (sda3_0) tioa7_2 ic21_1 rto24_0 (ppg24_0) - - 110 - p66 g h sin3_0 adtg_8 int11_2 ic22_1 rto23_0 (ppg22_0) - - 111 - p65 g i tiob7_0 sck5_1 (scl5_1) ic23_1 rto22_0 (ppg22_0) - - 112 - p64 g h tioa7_0 sot5_1 (sda5_1) int10_2 frck2_1 rto21_0 (ppg20_0)
document number: 002 - 08541 rev.*c page 25 of 117 mb9b510r s eries pin no pin name i/o circuit type pin state type lqfp - 100 fbga - 112 lqfp - 120 qfp - 100 93 d6 113 71 p63 g h int03_0 sin5_1 rx0_2 mwex_0 - - - rto20_0 (ppg20_0) 94 c5 114 72 p62 e i sck5_0 (scl5_0) adtg_3 tx0_2 m oex_0 95 b4 115 73 p61 e i sot5_0 (sda5_0) tiob2_2 uhconx 96 c4 116 74 p60 i * h sin5_0 tioa2_2 int15_1 mrdy_0 97 a4 117 75 usbvcc - 98 a3 118 76 p80 h o udm0 99 a2 119 77 p81 h o udp0 100 a1 120 78 vss - * : 5 v tolerant i/o
document number: 002 - 08541 rev.*c page 26 of 117 mb9b510r s eries list of pin functions the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 adc adtg_0 a/d converter external trigger input pin 84 a7 99 62 adtg_1 7 d3 7 85 adtg_2 18 f4 23 96 adtg_3 94 c5 114 72 adtg_4 - - 8 1 - adtg_5 70 d11 80 48 adtg_6 12 e4 17 90 adtg_7 30 j5 35 8 adtg_8 - - 110 - an00 a/d converter analog input pin . anxx describes adc ch.xx . 52 j11 62 30 an01 53 j10 63 31 an02 54 j8 64 32 an03 55 h10 65 33 an04 56 h9 66 34 an05 57 h7 67 35 an06 58 g10 68 36 an07 59 g9 69 37 an08 63 g8 73 41 an09 64 f10 74 42 an10 65 f9 75 43 an11 66 e11 76 44 an12 67 e10 77 45 an13 68 f8 78 46 an14 69 e9 79 47 an15 70 d11 80 48 base timer 0 tioa0_0 base timer ch.0 tioa pin 27 j4 32 5 tioa0_1 19 g3 24 97 tioa0_2 85 b7 100 63 tiob0_0 base timer ch.0 tiob pin 40 j6 45 18 tiob0_1 9 e1 14 87 tiob0_2 86 c7 101 64 base timer 1 tioa1_0 base timer ch.1 tioa pin 28 l5 33 6 tioa1_1 20 h1 25 98 tioa1_2 5 d1 5 83 tiob1_0 base timer ch.1 tiob pin 41 l7 46 19 tiob1_1 10 e2 15 88 tiob1_2 6 d2 6 84 base timer 2 tioa2_0 base timer ch.2 tioa pin 29 k5 34 7 tioa2_1 21 h2 26 99 tioa2_2 96 c4 116 74 tiob2_0 base timer ch.2 tiob pin 42 k7 47 20 tiob2_1 11 e3 16 89 tiob2_2 95 b4 115 73 base timer 3 tioa3_0 base timer ch.3 tioa pin 30 j5 35 8 tioa3_1 22 g4 27 100 tioa3_2 90 c6 105 68 tiob3_0 base timer ch.3 tiob pin 43 h6 48 21 tiob3_1 12 e4 17 90 tiob3_2 91 a5 106 69
document number: 002 - 08541 rev.*c page 27 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 base timer 4 tioa4_0 base timer ch.4 tioa pin 31 h5 36 9 tioa4_1 23 h3 28 1 tioa4_2 - - 51 - tiob4_0 base timer ch.4 tiob pin 44 j7 49 22 tiob4_1 13 f1 18 91 tiob4_2 - - 52 - base timer 5 tioa5_0 base timer ch.5 tioa pin 32 l6 37 10 tioa5_1 24 j2 29 2 tioa5_2 82 c8 97 60 tiob5_0 base timer ch.5 tiob pin 45 k8 50 23 tiob5_1 14 f2 19 92 tiob5_2 83 d9 98 61 base timer 6 tioa6_ 0 base timer ch.6 tioa pin - - 53 - tioa6_1 89 b6 104 67 tioa6_ 2 - - 82 - tiob6_ 0 base timer ch.6 tiob pin - - 54 - tiob6_1 88 a6 103 66 tiob6_ 2 - - 81 - base timer 7 tioa7_0 base timer ch.7 tioa pin - - 112 - tioa7_1 71 d10 86 49 tioa7_2 - - 109 - tiob7_0 base timer ch.7 tiob pin - - 111 - tiob7_1 72 e8 87 50 tiob7_2 - - 108 - can 0 tx0_0 can interface ch.0 tx output pin - - 51 - tx0_1 13 f1 18 91 tx0_2 94 c5 114 72 rx0_0 can interface ch.0 rx output pin - - 52 - rx0_1 14 f2 19 92 rx0_2 93 d6 113 71 can 1 tx1_0 can interface ch.1 tx output pin - - 84 - tx1_1 - - 12 - tx1_2 54 j8 64 32 rx1_0 can interface ch.1 rx output pin - - 85 - rx1_1 - - 11 - rx1_2 53 j10 63 31 debugger swclk serial wire debug interface clock input pin 78 b9 93 56 swdio serial wire debug interface data input / output pin 80 a8 95 58 swo serial wire viewer output pin 81 b8 96 59 tck jtag test clock input pin 78 b9 93 56 tdi jtag test data input pin 79 b11 94 57 tdo jtag debug data output pin 81 b8 96 59 tms jtag test mode state input/output pin 80 a8 95 58 traceclk trace clk output pin of etm 86 c7 101 64 traced0 trace data output pin of etm 82 c8 97 60 traced1 83 d9 98 61 traced2 84 a7 99 62 traced3 85 b7 100 63 trstx jtag test reset input pin 77 a9 92 55
document number: 002 - 08541 rev.*c page 28 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 external bus mad00 _0 external bus interface address bus 31 h5 36 9 mad01 _0 32 l6 37 10 mad02 _0 39 k6 44 17 mad03 _0 40 j6 45 18 mad04 _0 41 l7 46 19 mad05 _0 42 k7 47 20 mad06 _0 43 h6 48 21 mad07 _0 44 j7 49 22 mad08 _0 45 k8 50 23 mad09 _0 53 j10 63 31 mad10 _0 54 j8 64 32 mad11 _0 55 h10 65 33 mad12 _0 56 h9 66 34 mad13 _0 57 h7 67 35 mad14 _0 58 g10 68 36 mad15 _0 59 g9 69 37 mad16 _0 63 g8 73 41 mad17 _0 64 f10 74 42 mad18 _0 65 f9 75 43 mad19 _0 66 e11 76 44 mad20 _0 67 e10 77 45 mad21 _0 68 f8 78 46 mad22 _0 69 e9 79 47 mad23 _0 70 d11 80 48 mad24 _0 74 c10 89 52 mcsx0 _0 external bus interface chip select output pin 88 a6 103 66 mcsx1 _0 87 d7 102 65 mcsx2 _0 86 c7 101 64 mcsx3 _0 85 b7 100 63 mcsx4 _0 83 d9 98 61 mcsx5 _0 82 c8 97 60 mcsx6 _0 79 b11 94 57 mcsx7 _0 77 a9 92 55
document number: 002 - 08541 rev.*c page 29 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 external bus m a data0 _0 external bus interface data bus (address / data multiplex bus) 2 c1 2 80 m a data1 _0 3 c2 3 81 m a data2 _0 4 b3 4 82 m a data3 _0 5 d1 5 83 m a data4 _0 6 d2 6 84 m a data5 _0 7 d3 7 85 m a data6 _0 8 d5 8 86 m a data7 _0 9 e1 9 87 m a data8 _0 10 e2 10 88 m a data9 _0 11 e3 11 89 m a data10 _0 12 e4 12 90 m a data11 _0 13 f1 13 91 m a data12 _0 14 f2 14 92 m a data13 _0 15 f3 15 93 m a data14 _0 16 g1 16 94 m a data15 _0 17 g2 17 95 mdqm0 _0 external bus interface byte mask signal output pin 90 c6 105 68 mdqm1 _0 91 a5 106 69 male_0 external bus interface address latch enable output signal for multiplex 89 b6 104 67 mrdy_0 external bus interface external rdy input signal 96 c4 116 74 mclkout_0 external bus interface external clock output pin 84 a7 99 62 mnale _0 external bus interface ale signal to control nand flash output pin - - 18 - mncle _0 external bus interface cle signal to control nand flash output pin - - 19 - mnrex _0 external bus interface read enable signal to control nand flash - - 21 - mnwex _0 external bus interface write enable signal to control nand flash - - 20 - moex _0 external bus interface read enable signal for sram 94 c5 114 72 mwex _0 external bus interface write enable signal for sram 93 d6 113 71
document number: 002 - 08541 rev.*c page 30 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 external interrupt int00_0 external interrupt request 00 input pin 2 c1 2 80 int00_1 82 c8 97 60 int00_2 87 d7 102 65 int01_0 external interrupt request 01 input pin 3 c2 3 81 int01_1 83 d9 98 61 int01_2 - - 85 - int02_0 external interrupt request 02 input pin 4 b3 4 82 int02_1 53 j10 63 31 int02_2 - - 82 - int03_0 external interrupt request 03 input pin 93 d6 113 71 int03_1 56 h9 66 34 int03_2 9 e1 14 87 int04_0 external interrupt request 04 input pin 12 e4 17 90 int04_1 59 g9 69 37 int04_2 10 e2 15 88 int05_0 external interrupt request 05 input pin 74 c10 89 52 int05_1 65 f9 75 43 int05_2 11 e3 16 89 int06_1 external interrupt request 06 input pin 73 c11 88 51 int06_2 45 k8 50 23 int07_2 external interrupt request 07 input pin 5 d1 5 83 int08_1 external interrupt request 08 input pin 14 f2 19 92 int08_2 8 d5 8 86 int09_1 external interrupt request 09 input pin 15 f3 20 93 int09_2 - - 11 - int10_1 external interrupt request 10 input pin 16 g1 21 94 int10_2 - - 112 - int11_1 external interrupt request 11 input pin 17 g2 22 95 int11_2 - - 110 - int12_1 external interrupt request 1 2 input pin 27 j4 32 5 int12_2 - - 108 - int13_1 external interrupt request 1 3 input pin 28 l5 33 6 int13_2 - - 52 - int14_1 external interrupt request 1 4 input pin 39 k6 44 17 int14_2 - - 53 - int15_1 external interrupt request 1 5 input pin 96 c4 116 74 int15_2 - - 54 - nmix non - maskable interrupt input pin 92 b5 107 70
document number: 002 - 08541 rev.*c page 31 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 gpio p00 general - purpose i/o port 0 77 a9 92 55 p01 78 b9 93 56 p02 79 b11 94 57 p03 80 a8 95 58 p04 81 b8 96 59 p05 82 c8 97 60 p06 83 d9 98 61 p07 84 a7 99 62 p08 85 b7 100 63 p09 86 c7 101 64 p0a 87 d7 102 65 p0b 88 a6 103 66 p0c 89 b6 104 67 p0d 90 c6 105 68 p0e 91 a5 106 69 p0f 92 b5 107 70 p10 general - purpose i/o port 1 52 j11 62 30 p11 53 j10 63 31 p12 54 j8 64 32 p13 55 h10 65 33 p14 56 h9 66 34 p15 57 h7 67 35 p16 58 g10 68 36 p17 59 g9 69 37 p18 63 g8 73 41 p19 64 f10 74 42 p1a 65 f9 75 43 p1b 66 e11 76 44 p1c 67 e10 77 45 p1d 68 f8 78 46 p1e 69 e9 79 47 p1f 70 d11 80 48 p20 general - purpose i/o port 2 74 c10 89 52 p21 73 c11 88 51 p22 72 e8 87 50 p23 71 d10 86 49 p24 - - 85 - p25 - - 84 - p26 - - 83 - p27 - - 82 - p28 - - 81 -
document number: 002 - 08541 rev.*c page 32 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 gpio p30 general - purpose i/o port 3 9 e1 14 87 p31 10 e2 15 88 p32 11 e3 16 89 p33 12 e4 17 90 p34 13 f1 18 91 p35 14 f2 19 92 p36 15 f3 20 93 p37 16 g1 21 94 p38 17 g2 22 95 p39 18 f4 23 96 p3a 19 g3 24 97 p3b 20 h1 25 98 p3c 21 h2 26 99 p3d 22 g4 27 100 p3e 23 h3 28 1 p3f 24 j2 29 2 p40 general - purpose i/o port 4 27 j4 32 5 p41 28 l5 33 6 p42 29 k5 34 7 p43 30 j5 35 8 p44 31 h5 36 9 p45 32 l6 37 10 p46 36 l3 41 14 p47 37 k3 42 15 p48 39 k6 44 17 p49 40 j6 45 18 p4a 41 l7 46 19 p4b 42 k7 47 20 p4c 43 h6 48 21 p4d 44 j7 49 22 p4e 45 k8 50 23 p50 general - purpose i/o port 5 2 c1 2 80 p51 3 c2 3 81 p52 4 b3 4 82 p53 5 d1 5 83 p54 6 d2 6 84 p55 7 d3 7 85 p56 8 d5 8 86 p57 - - 9 - p58 - - 10 - p59 - - 11 - p5a - - 12 - p5b - - 13 -
document number: 002 - 08541 rev.*c page 33 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 gpio p60 general - purpose i/o port 6 96 c4 116 74 p61 95 b4 115 73 p62 94 c5 114 72 p63 93 d6 113 71 p64 - - 112 - p65 - - 111 - p66 - - 110 - p67 - - 109 - p68 - - 108 - p70 general - purpose i/o port 7 - - 51 - p71 - - 52 - p72 - - 53 - p73 - - 54 - p74 - - 55 - p80 general - purpose i/o port 8 98 a3 118 76 p81 99 a2 119 77 pe0 general - purpose i/o port e 46 k9 56 24 pe2 48 l9 58 26 pe3 49 l10 59 27 multi - f unction serial 0 sin0_0 multi - function serial interface ch.0 input pin 73 c11 88 51 sin0_1 56 h9 66 34 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 72 e8 87 50 sot0_1 (sda0_1) 57 h7 67 35 sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as scl0 when it is used in an i 2 c (operation mode 4). 71 d10 86 49 sck0_1 (scl0_1) 58 g10 68 36 multi - f unction serial 1 sin1_0 multi - function serial interface ch.1 input pin - - 8 - sin1_1 53 j10 63 31 sot1_0 (sda1_0) multi - function serial interface ch.1 output pin. this pin operates as sot1 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda1 when it is used in an i 2 c (operation mode 4). - - 9 - sot1_1 (sda1_1) 54 j8 64 32 sck1_0 (scl1_0) multi - function serial interface ch.1 clock i/o pin. this pin operates as sck1 when it is used in a csio (operation modes 4 ) and as scl1 when it is used in an i 2 c (operation mode 4). - - 10 - sck1_1 (scl1_1) 55 h10 65 33
document number: 002 - 08541 rev.*c page 34 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction serial 2 sin2_0 multi - function serial interface ch.2 input pin - - 53 - sin2_1 - - 85 - sin2_2 59 g9 69 37 sot2_0 (sda2_0) multi - function serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). - - 54 - sot2_1 (sda2_1) - - 84 - sot2_2 (sda2_2) 63 g8 73 41 sck2_0 (scl2_0) multi - function serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a csio (operation modes 2 ) and as scl2 when it is used in an i 2 c (operation mode 4). - - 55 - sck2_1 (scl2_1) - - 83 - sck2_2 (scl2_2) 64 f10 74 42 multi - f unction serial 3 sin3_0 multi - function serial interface ch.3 input pin - - 110 - sin3_1 2 c1 2 80 sin3_2 39 k6 44 17 sot3_0 (sda3_0) multi - function serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda3 when it is used in an i 2 c (operation mode 4). - - 109 - sot3_1 (sda3_1) 3 c2 3 81 sot3_2 (sda3_2) 40 j6 45 18 sck3_0 (scl3_0) multi - function serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a csio (operation modes 2 ) and as scl3 when it is used in an i 2 c (operation mode 4). - - 108 - sck3_1 (scl3_1) 4 b3 4 82 sck3_2 (scl3_2) 41 l7 46 19 multi - f unction serial 4 sin4_0 multi - function serial interface ch.4 input pin 87 d7 102 65 sin4_1 65 f9 75 43 sin4_2 82 c8 97 60 sot4_0 (sda4_0) multi - function serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda4 when it is used in an i 2 c (operation mode 4). 88 a6 103 66 sot4_1 (sda4_1) 66 e11 76 44 sot4_2 (sda4_2) 83 d9 98 61 sck4_0 (scl4_0) multi - function serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a csio (operation modes 2 ) and as scl4 when it is used in an i 2 c (operation mode 4). 89 b6 104 67 sck4_1 (scl4_1) 67 e10 77 45 sck4_2 (scl4_2) 84 a7 99 62 rts4_0 multi - function serial interface ch.4 rts output pin 90 c6 105 68 rts4_1 69 e9 79 47 rts4_2 86 c7 101 64 cts4_0 multi - function serial interface ch.4 cts input pin 91 a5 106 69 cts4_1 68 f8 78 46 cts4_2 85 b7 100 63
document number: 002 - 08541 rev.*c page 35 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction serial 5 sin5_0 multi - function serial interface ch.5 input pin 96 c4 116 74 sin5_1 93 d6 113 93 sin5_2 15 f3 20 93 sot5_0 (sda5_0) multi - function serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 95 b4 115 73 sot5_1 (sda5_1) - - 112 - sot5_2 (sda5_2) 16 g1 21 94 sck5_0 (scl5_0) multi - function serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a csio (operation modes 2 ) and as scl5 when it is used in an i 2 c (operation mode 4). 94 c5 114 72 sck5_1 (scl5_1) - - 111 - sck5_2 (scl5_2) 17 g2 22 95 multi - f unction serial 6 sin6_0 multi - function serial interface ch.6 input pin 5 d1 5 83 sin6_1 12 e4 17 90 sot6_0 (sda6_0) multi - function serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda6 when it is used in an i 2 c (operation mode 4). 6 d2 6 84 sot6_1 (sda6_1) 11 e3 16 89 sck6_0 (scl6_0) multi - function serial interface ch.6 clock i/o pin. this pin operates as sck6 when it is used in a csio (operation modes 2 ) and as scl6 when it is used in an i 2 c (operation mode 4). 7 d3 7 85 sck6_1 (scl6_1) 10 e2 15 88 multi - f unction serial 7 sin7_0 multi - function serial interface ch.7 input pin - - 11 - sin7_1 45 k8 50 23 sot7_0 (sda7_0) multi - function serial interface ch.7 output pin. this pin operates as sot7 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda7 when it is used in an i 2 c (operation mode 4). - - 12 - sot7_1 (sda7_1) 44 j7 49 22 sck7_0 (scl7_0) multi - function serial interface ch.7 clock i/o pin. this pin operates as sck7 when it is used in a csio (operation modes 2 ) and as scl7 when it is used in an i 2 c (operation mode 4). - - 13 - sck7_1 (scl7_1) 43 h6 48 21
document number: 002 - 08541 rev.*c page 36 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction timer 0 dtti0x_0 input signal controlling wave form generator outputs rto00 to rto05 of multi - function timer 0. 18 f4 23 96 dtti0x_1 69 e9 79 47 frck0_0 16 - bit free - run timer ch.0 external clock input pin 13 f1 18 91 frck0_1 70 d11 80 48 frck0_ 2 53 j10 63 31 ic00_0 16 - bit input capture ch.0 input pin of multi - function timer 0 . icxx describes chan n el number. 17 g2 22 95 ic00_1 65 f9 75 43 ic00_ 2 54 j8 64 32 ic01_0 16 g1 21 94 ic01_1 66 e11 76 44 ic01_ 2 55 h10 65 33 ic02_0 15 f3 20 93 ic02_1 67 e10 77 45 ic 02_ 2 56 h9 66 34 ic03_0 14 f2 19 92 ic03_1 68 f8 78 46 ic03_ 2 57 h7 67 35 rto00_0 (ppg00_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output modes. 19 g3 24 97 rto00_1 (ppg00_1) - - 86 - rto01_0 (ppg00_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output modes. 20 h1 25 98 rto01_1 (ppg00_1) - - 85 - rto02_0 (ppg02_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output modes. 21 h2 26 99 rto02_1 (ppg02_1) - - 84 - rto03_0 (ppg02_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output modes. 22 g4 27 100 rto03_1 (ppg02_1) - - 83 - rto04_0 (ppg04_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output modes. 23 h3 28 1 rto04_1 (ppg04_1) - - 82 - rto05_0 (ppg04_0) wave form generator output pin of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output modes. 24 j2 29 2 rto05_1 (ppg04_1) - - 81 -
document number: 002 - 08541 rev.*c page 37 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction timer 1 dtti1x_0 input signal controlling wave form generator outputs rto10 to rto15 of multi - function timer 1. 8 d5 8 86 dtti1x_1 39 k6 44 17 frck1_0 16 - bit free - run timer ch.1 external clock input pin 87 d7 102 65 frck1_1 44 j7 49 22 ic10_0 16 - bit input capture ch.1 input pin of multi - function timer 1. icxx describes chan n el number . 88 a6 103 66 ic10_1 40 j6 45 18 ic11_0 89 b6 104 67 ic11_1 41 l7 46 19 ic12_0 90 c6 105 68 ic12_1 42 k7 47 20 ic13_0 91 a5 106 69 ic13_1 43 h6 48 21 rto10_0 (ppg10_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 2 c1 2 80 rto10_1 (ppg10_1) 27 j4 32 5 rto11_0 (ppg10_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 3 c2 3 81 rto11_1 (ppg10_1) 28 l5 33 6 rto12_0 (ppg12_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg12 when it is used in ppg1 output modes. 4 b3 4 82 rto12_1 (ppg12_1) 29 k5 34 7 rto13_0 (ppg12_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg12 when it is used in ppg1 output modes. 5 d1 5 83 rto13_1 (ppg12_1) 30 j5 35 8 rto14_0 (ppg14_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 6 d2 6 84 rto14_1 (ppg14_1) 31 h5 36 9 rto15_0 (ppg14_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 7 d3 7 85 rto15_1 (ppg14_1) 32 l6 37 10
document number: 002 - 08541 rev.*c page 38 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 multi - f unction timer 2 dtti 2 x_0 input signal controlling wave form generator outputs rto20 to rto25 of multi - function timer 2. 92 b5 107 70 dtti 2 x_1 92 b5 107 70 frck 2 _0 16 - bit free - run timer ch.2 external clock input pin 87 d7 102 65 frck 2 _1 - - 112 - ic 2 0_0 16 - bit input capture ch.2 input pin of multi - function timer 2. icxx describes chan n el number. 88 a6 103 66 ic 2 0_1 - - 108 - ic 2 1_0 89 b6 104 67 ic 2 1_1 - - 109 - ic 2 2_0 90 c6 105 68 ic 2 2_1 - - 110 - ic 2 3_0 91 a5 106 69 ic 2 3_1 - - 111 - rto 2 0_0 (ppg2 0_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg20 when it is used in ppg2 output modes. - - 113 - rto 2 0_1 (ppg2 0_1) 86 c7 101 64 rto 2 1_0 (ppg 2 0_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg20 when it is used in ppg2 output modes. - - 112 - rto 2 1_1 (ppg 2 0_1) 87 d7 102 65 rto 2 2_0 (ppg2 2_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg22 when it is used in ppg2 output modes. - - 111 - rto 2 2_1 (ppg2 2_1) 88 a6 103 66 rto 2 3_0 (ppg2 2_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg22 when it is used in ppg2 output modes. - - 110 - rto 2 3_1 (ppg2 2_1) 89 b6 104 67 rto 2 4_0 (ppg2 4_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg24 when it is used in ppg2 output modes. - - 109 - rto 2 4_1 (ppg2 4_1) 90 c6 105 68 rto 2 5_0 (ppg2 4_0) wave form generator output pin of multi - function timer 2. this pin operates as ppg24 when it is used in ppg2 output modes. - - 108 - rto 2 5_1 (ppg2 4_1) 91 a5 106 69 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 9 e1 14 87 ain0_1 40 j6 45 18 ain0_2 2 c1 2 80 bin0_0 qprc ch.0 bin input pin 10 e2 15 88 bin0_1 41 l7 46 19 bin0_2 3 c2 3 81 zin0_0 qprc ch.0 zin input pin 11 e3 16 89 zin0_1 42 k7 47 20 zin0_2 4 b3 4 82 quadrature position/ revolution counter 1 ain1_1 qprc ch.1 ain input pin 74 c10 89 52 ain1_2 43 h6 48 21 bin1_1 qprc ch.1 bin input pin 73 c11 88 51 bin1_2 44 j7 49 22 zin1_1 qprc ch.1 zin input pin 72 e8 87 50 zin1_2 45 k8 50 23
document number: 002 - 08541 rev.*c page 39 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 quadrature position/ revolution counter 2 ain2_0 qprc ch.2 ain input pin - - 10 - ain2_1 83 d9 98 61 bin2_0 qprc ch.2 bin input pin - - 11 - bin2_1 84 a7 99 62 zin2_0 qprc ch.2 zin input pin - - 12 - zin2_1 85 b7 100 63 real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 92 b5 107 70 rtcco_1 55 h10 65 33 rtcco_2 19 g3 24 97 subout_0 sub clock output pin 92 b5 107 70 subout_1 55 h10 65 33 subout_2 19 g3 24 97 usb udm0 usb device /host d C pin 98 a3 118 76 udp0 usb device /host d + pin 99 a2 119 77 uhconx usb external pull - up control pin 95 b4 115 73 r eset initx external reset input pin . a reset is valid when initx="l". 38 k4 43 16 mode md0 mode 0 pin. during normal operation, md0="l" must be input. during serial programming to f lash memory, md0="h" must be input. 47 l8 57 25 md1 mode 1 pin. during serial programming to f lash memory, md1="l" must be input. 46 k9 56 24 p ower vcc power supply pin 1 b1 1 79 vcc power supply p in 26 j1 31 4 vcc power supply pin 35 k1 40 13 vcc power supply pin 51 k11 61 29 vcc power supply pin 76 a10 91 54 usbvcc 3.3v power supply port for usb i/o 97 a4 117 75 gnd vss gnd pin - b2 - vss gnd pin 25 l1 30 3 vss gnd pin - k2 - vss gnd pin - j3 - vss gnd pin - h4 - vss gnd pin 34 l4 39 12 vss gnd pin 50 l11 60 28 vss gnd pin - k10 - vss gnd pin - j9 - vss gnd pin - h8 - vss gnd pin - b10 - vss gnd pin - c9 - vss gnd pin 75 a11 90 53 vss gnd pin - d8 - vss gnd pin - d4 - vss gnd pin - c3 - vss gnd pin 100 a1 120 78
document number: 002 - 08541 rev.*c page 40 of 117 mb9b510r s eries module pin name function pin no lqfp - 100 fbga - 1 12 lqfp - 120 qfp - 1 00 c lock x0 main clock (oscillation) input pin 48 l9 58 26 x0a sub clock (oscillation) input pin 36 l3 41 14 x1 main clock (oscillation) i/o pin 49 l10 59 27 x1a sub clock (oscillation) i/o pin 37 k3 42 15 crout _0 built - in high - speed cr - osc clock output port 74 c10 89 52 crout _1 92 b5 107 70 analog p ower avcc a/d converter analog power pin 60 h11 70 38 avrh a/d converter analog reference voltage input pin 61 f11 71 39 analog gnd avss a/d converter gnd pin 62 g11 72 40 c pin c power stabilization capacity pin 33 l2 38 11 note : ? while this device contains a test access port (tap) based on the ieee 1149.1 - 2001 jtag standard, it is not fully compliant to all requirements of that standard. this device may contain a 32 - bit device id that is the same as the 32 - bit device id in other devices with different functionality. the tap pins may also be configurable for purposes other than access to the tap controller.
document number: 002 - 08541 rev.*c page 41 of 117 mb9b510r s eries 5. i/o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma b ? cmos level hysteresis input ? pull - up resistor : approximately 50 k p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control pull - up resistor digital in put
document number: 002 - 08541 rev.*c page 42 of 117 mb9b510r s eries type circuit remarks c ? open drain output ? cmos level hysteresis input d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital input digital out put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control n-ch
document number: 002 - 08541 rev.*c page 43 of 117 mb9b510r s eries type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output ? p - ch transistor is always off ? +b input is available f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i2c pin, the digital output ? p - ch transistor is always off ? +b input is available digital output digital output pull - up resistor control digital input standby mode control digital output digital output pull - up resistor control digital input standby mode control analog input input control p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 08541 rev.*c page 44 of 117 mb9b510r s eries type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? +b input is available h it is possible to select the usb i/o / gpio function. when the usb i/o is selected ? full - speed, low - speed control when the gpio is selected. ? cmos level output ? cmos level hysteresis input ? with standby mode control ? i oh = - 20.5 ma, i ol = 18.5 ma digital output digital output pull - up resistor control digital input standby mode control gpio digital output gpio digital input/output direction gpio digital input gpio digital input circuit control udp output usb full - speed/low - speed control udp input differential input usb/gpio select udm input udm output usb digital input/output direction gpio digital input gpio digital input/output direction gpio digital input gpio digital input circuit control p-ch p-ch n-ch r udp/pxx udm/pxx di f ferential
document number: 002 - 08541 rev.*c page 45 of 117 mb9b510r s eries type circuit remarks i ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? 5 v tolerant ? with standby mode control ? i oh = - 4 ma, i ol = 4 ma ? available to control of pzr registers. ? when this pin is used as an i2c pin, the digital output p - ch transistor is always off j cmos level hysteresis input mode input digital output digital output pull - up resistor control digital input standby mode control p-ch p-ch n-ch r
document number: 002 - 08541 rev.*c page 46 of 117 mb9b510r s eries 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the co nditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating co nditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operati ng conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering applicat ion outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such conditions if pre sent for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connect ed through an appropriate resistance to a power supply pin or ground pin. latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn juncti ons (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of relia bility in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include atten tion to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence.
document number: 002 - 08541 rev.*c page 47 of 117 mb9b510r s eries observance of safety regulations and standards most countries in the world have established standards and regulations regarding s afety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. precautio ns related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.) . caution: customers considering the use of our products in special applications where failure or abnormal operation may direct ly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (s u ch as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life suppo rt, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages a rising from such use without prior approval. 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress ' recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually caus es leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket c ontacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. surface mount type surface mount packaging has long er and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to op en connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. lead - free packaging caution: when ball grid array ( fbga ) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use.
document number: 002 - 08541 rev.*c page 48 of 117 mb9b510r s eries storage of semiconductor d evices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel , reducing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temp eratures between 5c and 30c. when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semicondu ctor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. ba king packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125c/24 h static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder ve ssels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies.
document number: 002 - 08541 rev.*c page 49 of 117 mb9b510r s eries 6.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, con sider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, f lame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 08541 rev.*c page 50 of 117 mb9b510r s eries 7. handling devices power supply pins in products with multiple vcc and vss pins, respective pins at the same potential are interconnected within the device in ord er to prevent malf unctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the ground le vel, and to conform to the total output current rating. moreover, connect the current supply source with each power pins and gnd pins of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connected as a b ypass capacitor between each power supply pin and gnd pin, between avcc pin and avss pin near this device. stabilizing power supply voltage a malfunction may occur w hen the power supply voltage fluctuates rapidly even though the fluctuation is within the r ecommended operating conditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10 % of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the po wer supply. crystal oscillator circuit noise near the x0/x1 and x0a/x1a pins may cause the device to malfunction. design the printed circuit board so that x0/x1, x0a/x1a pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0/x1 and x0a/x1a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. using an external clock w hen using an external clock, the clock signal should be input to the x0, x0a pin only and the x1, x1a pin should be kept open . handling when using multi function serial pin as i 2 c pin if it is using multi function serial pin as i2c pins, p - ch transistor of digital output is always disable. however, i2c pins need to keep the electrical characteristic like other pins and not to connect to external i2c bus system with power off. ? example of using an external clock device x0(x0a) x1(x1a) open
document number: 002 - 08541 rev.*c page 51 of 117 mb9b510r s eries c pin this series contains the regulator. be sure to connect a smoothing capacitor (cs) for the regulator between the c pin and the gnd pin. please use a ceramic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. how ever, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristics). please select the capacitor that meets the specifications in the operating conditio ns to use b y evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. mode pins (md0) connect the md pin (md0) directly to vcc or vss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and vcc pins or vss pins is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switchin g the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise. notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter, co nnect avcc = vcc and avss = vss. turning on: vcc serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected, retransmit the data. differences in features among the products with different memory sizes and between flash products and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with dif ferent memory sizes and between flash products and mask products are different because chip layout and memory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteri stics. pull - up function of 5 v tolerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5 v tolerant i/o. device c vss c s gnd
document number: 002 - 08541 rev.*c page 52 of 117 mb9b510r s eries 8. block diagram 9. memory size see " 1 product lineup " of " memory size" to confirm the memory size. m a i n f l a s h i / f c o r t e x - m 3 c o r e 1 4 4 m h z ( m a x ) c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . m u l t i - f u n c t i o n t i m e r x 3 m u l t i - f u n c t i o n s e r i a l i / f 8 c h . ( w i t h f i f o c h . 4 - c h . 7 ) h w f l o w c o n t r o l ( c h . 4 ) 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . w a v e f o r m g e n e r a t o r 3 c h . a / d a c t i v a t i o n c o m p a r e 3 c h . 1 6 - b i t p p g 3 c h . w a t c h c o u n t e r u n i t 0 g p i o c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 - p i n + n m i t p i u r o m t a b l e e t m s r a m 0 8 / 1 6 / 2 4 / 3 2 k b y t e s w j - d p s r a m 1 8 / 1 6 / 2 4 / 3 2 k b y t e i d s y s m b 9 b f 5 1 2 n / r , m b 9 b f 5 1 4 n / r , m b 9 b f 5 1 5 n / r , m b 9 b f 5 1 6 n / r b a s e t i m e r 1 6 - b i t 8 c h . / 3 2 - b i t 4 c h . n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y 1 2 - b i t a / d c o n v e r t e r 3 u n i t 1 u n i t 2 t r s t x , t c k , t d i , t m s t r a c e d [ 3 : 0 ] , t r a c e c l k a v c c , a v s s , a v r h a n [ 1 5 : 0 0 ] t i o a [ 7 : 0 ] t i o b [ 7 : 0 ] i c 0 [ 3 : 0 ] d t t i [ 2 : 0 ] x r t o 0 [ 5 : 0 ] f r c k [ 2 : 0 ] t d o s c k [ 7 : 0 ] s i n [ 7 : 0 ] s o t [ 7 : 0 ] i n t [ 1 5 : 0 0 ] n m i x p 0 [ f : 0 ] , p 1 [ f : 0 ] , . . . p x [ x : 0 ] i n i t x m o d e - c t r l i r q - m o n i t o r p i n - f u n c t i o n - c t r l m d [ 1 : 0 ] q p r c 3 c h . a i n [ 2 : 0 ] b i n [ 2 : 0 ] z i n [ 2 : 0 ] l v d c t r l c r c a c c e l e r a t o r i c 1 [ 3 : 0 ] a d t g [ 8 : 0 ] r t s 4 c t s 4 e x t e r n a l b u s i / f m a d [ 2 4 : 0 0 ] m a d a t a [ 1 5 : 0 0 ] m c s x [ 7 : 0 ] , m a l e , m o e x , m w e x , m n a l e , m n c l e , m n w e x , m n r e x , m d q m [ 1 : 0 ] r t o 1 [ 5 : 0 ] u s b 2 . 0 ( h o s t / d e v i c e ) p h y u d p 0 , u d m 0 u s b v c c u h c o n x u s b c l o c k c t r l p l l m p u t r a c e b u f f e r ( 1 6 k b y t e ) i c 2 [ 3 : 0 ] r t o 2 [ 5 : 0 ] t x 1 , r x 1 c a n t x 0 , r x 0 c a n m a i n f l a s h 1 2 8 k b y t e / 2 5 6 k b y t e / 3 8 4 k b y t e / 5 1 2 k b y t e l v d p o w e r o n r e s e t r e g u l a t o r c w o r k f l a s h 3 2 k b y t e w o r k f l a s h i / f a h b - a h b b r i d g e c a n p r e s c a l e r r e a l - t i m e c l o c k r t c c o s u b o u t m r d y x 0 x 1 x 0 a p l l c l k c r 1 0 0 k h z s o u r c e c l o c k c r o u t m a i n o s c s u b o s c c r 4 m h z a h b - a p b b r i d g e : a p b 0 ( m a x 7 2 m h z ) m u l t i - l a y e r a h b ( m a x 1 4 4 m h z ) a h b - a p b b r i d g e : a p b 1 ( m a x 7 2 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 7 2 m h z ) x 1 a
document number: 002 - 08541 rev.*c page 53 of 117 mb9b510r s eries 10. memory map memory map (1) perip herals area 0x41ff_ffff reserved 0x4006_4000 0x4006_3000 can ch.1 0x4006_2000 can ch.0 0x4006_1000 reserved 0x4006_0000 dmac 0x4005_0000 reserved 0x4004_0000 usb ch.0 0x4003_f000 ext - bus i/f 0x4003_c000 reserved 0x4003_b000 rtc 0x4003_a000 watch counter 0x4003_9000 crc 0x4003_8000 mfs 0x4003_7000 can prescaler 0x4003_ 6 000 usb clock ctrl 0x4003_5000 lvd ctrl 0x4003_4000 reserved 0x4003_ 3 000 gpio 0x4003_2000 reserved 0x4003_1000 int - req. read 0x4003_0000 exti 0x4002_f000 reserved 0x4002_e000 cr trim 0x4002_8000 reserved 0x4002_7000 a/dc 0x4002_6000 qprc 0x4002_5000 base timer 0x4002_4000 ppg 0x4002_3000 reserved 0x4002_2000 mft unit2 0x4002_1000 mft unit1 0x4002_0000 mft unit0 0x4001_6000 reserved 0x4001_5000 dual timer 0x4001_3000 reserved 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 reserved 0x4000_0000 mainflash i/f 0xffff_ffff reserved 0xe010_0000 0xe000_0000 cortex - m3 private peripherals 0x 7 000_0000 reserved 0x6000_0000 external device area 0x4400_0000 reserved 0x4200_0000 32mbyte bit band alias 0x4000_0000 peripherals 0x2400_0000 reserved 0x2200_0000 32mbyte bit band alias 0x200e_1000 reserved see the next page " ? memory map (2), (3)" for the memory size deta i ls . 0x200e_0000 workflash i / f 0x200c_0000 workflash 0x2008_0000 reserved 0x2000_0000 sram1 0x1fff_0000 sram0 0x0010_2000 reserved 0x0010_0000 security/cr trim 0x00 0 0_0000 mainflash
document number: 002 - 08541 rev.*c page 54 of 117 mb9b510r s eries memory map (2) see "mb9b510r/410r/310r/110r series flash programming manual" for sector structure of flash. mb9bf51 6 n/r 0x200e_0000 reserved workflash 32kbyte 0x200 c _ 8 000 0x200 c _ 0 000 sa0 - 3 (8kbx4) 0x2000_8000 reserved 0x2000_0000 sram1 32kbyte 0x1fff_8000 sram0 32kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 security 0x0008_0000 reserved 0x0000_0000 sa10 - 15 (64kbx6) mainflash 512kbyte sa8 - 9 (48kbx2) sa4 - 7 (8kbx4) mb9bf515n/r 0x200e_0000 reserved workflash 32kbyte 0x200c_ 8 000 0x200c_0000 sa0 - 3 (8kbx4) 0x2000_6000 reserved 0x200 0 _0000 sram1 24kbyte 0x 1fff _ a 000 sram0 24kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 security 0x0006_0000 reserved 0x0000_0000 sa10 - 13 (64kbx4) mainflash 384 kbyte sa8 - 9 (48kbx2) sa4 - 7 (8kbx4)
document number: 002 - 08541 rev.*c page 55 of 117 mb9b510r s eries memory map (3) see "mb9b510r/410r/310r/110r series flash programming manual" for sector structure of flash. mb9bf514n/r 0x200e_0000 reserved workflash 32kbyte 0x200c_ 8 000 0x200c_0000 sa0 - 3 (8kbx4) 0x2000_4000 reserved 0x2000_0000 sram1 16kbyte 0x1fff_c000 sram0 16 kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 security 0x0004_0000 reserved 0x0000_0000 sa10 - 11 (64kbx2) mainflash 256 kbyte sa8 - 9 (48kbx2) sa4 - 7 (8kbx4) mb9bf512n/r 0x200e_0000 reserved workflash 32kbyte 0x200c_ 8 000 0x200c_0000 sa0 - 3 (8kbx4) 0x2000_2000 reserved 0x2000_0000 sram1 8kbyte 0x1fff_e000 sram0 8kbyte 0x0010_2000 reserved 0x0010_1000 cr trimming 0x0010_0000 security 0x0002_0000 reserved 0x0000_0000 sa8 - 9 (48kbx2) mainflash 128 kbyte sa4 - 7 (8kbx4)
document number: 002 - 08541 rev.*c page 56 of 117 mb9b510r s eries peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb main flash i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit 0 0x4002_1000 0x4002_1fff multi - function timer unit 1 0x4002_2000 0x4002_3fff multi - function timer unit2 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff internal cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt controller 0x4003_1000 0x4003_1fff interrupt request batch - read function 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_5fff low - voltage detector 0x4003_6000 0x4003_6fff usb clock generator 0x4003_7000 0x4003_7fff can prescaler 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_ b fff real - time clock 0x4003_ c 000 0x4003_efff reserved 0x4003_f000 0x4003_ffff external memory interface 0x4004_0000 0x4004_ffff ahb usb ch . 0 0x4005_0000 0x4005_ffff reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_1000 0x4006_1fff reserved 0x4006_2000 0x4006_2fff can ch.0 0x4006_3000 0x4006_3fff can ch.1 0x4006_4000 0x41ff_ffff reserved 0x200e_0000 0x200e_ffff workflash i/f register
document number: 002 - 08541 rev.*c page 57 of 117 mb9b510r s eries 11. pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the "l" level. ? initx=1 this is the period when the initx pin is the "h" level. ? spl=0 this is the status that standby pin level setting bit (spl) in standby mode control register (stb_ctl) is set to "0". ? spl=1 this is the status that standby pin level setting bit (spl) in standby mode control register (stb_ctl) is set to "1". ? input enabled indic ates that the input function can be used. ? internal input fixed at "0" this is the status that the input function cannot be used. internal input is fixed at "l". ? hi - z indicates that the output drive transistor is disabled and the pin is put in the hi - z stat e. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used.
document number: 002 - 08541 rev.*c page 58 of 117 mb9b510r s eries list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " main crystal oscillator output pin hi - z/ internal input fixed at " 0 " / or input enable hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop* 1 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop* 1 / internal input fixed at " 0 " c initx input pin pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled pull - up/ input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled e jtag selected hi - z pull - up/ input enabled pull - up/ input enabled maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z/ internal input fixed at " 0 " f trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output external interrupt enabled selected maintain previous state gpio selected, or other than above resource selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " g trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected, or other than above resource selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 "
document number: 002 - 08541 rev.*c page 59 of 117 mb9b510r s eries pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 h external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or other than above resource selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " i gpio selected, resource selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " j nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected, or other than above resource selected hi - z hi - z/ input enabled hi - z/ input enabled hi - z/ internal input fixed at " 0 " k analog input selected hi - z hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled gpio selected, or other than above resource selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " l external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state analog input selected hi - z hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled hi - z/ internal input fixed at " 0 " / analog input enabled gpio selected, or other than above resource selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 "
document number: 002 - 08541 rev.*c page 60 of 117 mb9b510r s eries pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode or sleep mode state power supply unstable power supply stable power supply stable power supply stable - initx=0 initx=1 initx=1 initx=1 - - - - spl=0 spl=1 m gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator input pin input enabled input enabled input enabled input enabled input enabled input enabled n gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " sub crystal oscillator output pin hi - z/ internal input fixed at " 0 " / or input enable hi - z/ internal input fixed at " 0 " hi - z/ internal input fixed at " 0 " maintain previous state maintain previous state/ hi - z at oscillation stop* 2 / internal input fixed at " 0 " maintain previous state/ hi - z at oscillation stop* 2 / internal input fixed at " 0 " o gpio selected hi - z hi - z/ input enabled hi - z/ input enabled maintain previous state maintain previous state hi - z/ internal input fixed at " 0 " usb i/o pin setting disabled setting disabled setting disabled maintain previous state hi - z at transmission/ input enabled/ internal input fixed at " 0 " at reception hi - z at transmission/ input enabled/ internal input fixed at " 0 " at reception p mode input pin input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z/ input enabled *1: oscillation is stopped at sub timer mode, low - speed cr timer mode, and stop mode. *2: oscillation is stopped at stop mode.
document number: 002 - 08541 rev.*c page 61 of 117 mb9b510r s eries 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage* 1, * 2 v cc v ss - 0.5 v ss + 6.5 v power supply voltage (for usb)* 1, * 3 usbv cc v ss - 0.5 v ss + 6.5 v analog power supply voltage* 1, * 4 av cc v ss - 0.5 v ss + 6.5 v analog reference voltage* 1, * 4 avrh v ss - 0.5 v ss + 6.5 v input voltage* 1 v i v ss - 0.5 v cc + 0.5 ( 6.5 v) v except for usb pin v ss - 0.5 usb v cc + 0.5 ( 6.5 v) v usb pin v ss - 0.5 v ss + 6.5 v 5 v tolerant analog pin input voltage* 1 v ia v ss - 0.5 a v cc + 0.5 ( 6.5 v) v output voltage* 1 v o v ss - 0.5 v cc + 0.5 ( 6.5 v) v clamp maximum current i clamp - 2 +2 ma *8 clamp total maximum current [i clamp ] +20 ma *8 l level maximum output current* 5 i ol - 10 ma 4 ma type 20 ma 12 ma type 39 ma p80, p81 l level average output current* 6 i olav - 4 ma 4 ma type 12 ma 12 ma type 18.5 ma p80, p81 l level total maximum output current i ol - 100 ma l level total average output current* 7 i olav - 50 ma h level maximum output current* 5 i oh - - 10 ma 4 ma type - 20 ma 12 ma type - 39 ma p80, p81 h level average output current* 6 i ohav - - 4 ma 4 ma type - 12 ma 12 ma type - 20.5 ma p80, p81 h level total maximum output current i oh - - 100 ma h level total average output current* 7 i ohav - - 50 ma power consumption p d - 1000 mw storage temperature t stg - 55 + 150 c *1: these parameters are based on the condition that v ss = av ss = 0.0 v. *2: v cc must not drop below v ss - 0.5 v. *3: usbv cc must not drop below v ss - 0.5 v. *4: ensure that the voltage does not to exceed v cc + 0.5 v, for example, when the power is turned on. *5: the maximum output current is the peak value for a single pin. *6: the a verage output is the average current for a single pin over a period of 100 ms. *7: the total average output current is the average current for all pins over a period of 100 ms.
document number: 002 - 08541 rev.*c page 62 of 117 mb9b510r s eries *8: ? see "list of pin functions" and "i/o circuit type" about +b input availabl e pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input. ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the device pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consump t ion modes, the +b input p otential may pass through the protective diode and increase the potential at the vcc and avcc pin, and this may affect other devices. ? note that if a +b signal is input when the device power supply is off (not fixed at 0 v), the power supply is provided fr om the pins, so that incomplete operation may result. ? the following is a recommended circuit example (i/o equivalent circuit). warning : ? semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. r +b input (0v to 16v) protection diode p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output
document number: 002 - 08541 rev.*c page 63 of 117 mb9b510r s eries 12.2 recommended operating conditions (v ss = av ss = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage v cc - 2.7 5.5 v power supply voltage for usb ch.0 usbv cc - 3.0 3.6 ( cc ) v *1 2.7 5.5 ( cc ) *2 analog power supply voltage a v cc - 2.7 5.5 v av cc = v cc analog reference voltage avrh - 2.7 av cc v smoothing capacitor c s - 1 10 f 3 operating t emperature lqi100 lqm120 t a when mounted on four - layer pcb - 40 + 85 c pqh100 lbc112 t a - - 40 + 85 c *1: when p81/udp0 and p80/udm0 pin are used as usb (udp0, udm0). *2: when p81/udp0 and p80/udm0 pin are used as gpio (p81, p80). *3 : see "c pin" in "7 handling devices" for the connection of the smoothing capacitor. *4 : in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr(including main pll is used) or built - in low - speed cr is possible to operate only. warning : ? the recommend ed operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. ? always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditio ns, or combinations not represented on the data sh eet. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: 002 - 08541 rev.*c page 64 of 117 mb9b510r s eries 12.3 dc characteristics 12.3.1 current rating (v cc = av cc = usbv cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks typ * 3 max * 4 run mode current i cc v cc pll r un mode cpu: 144 mhz , peripheral: 72 mhz , main flash 2 wait tracebuffer: on frwtr.rwt = 10 fsyndn.sd = 000 fbfcr.be = 1 85 117 ma *1 , *5 cpu: 72 mhz , peripheral: 72 mhz , main flash 0 wait tracebuffer: off frwtr.rwt = 00 fsyndn.sd = 000 fbfcr.be = 0 52 70 ma *1 , *5 high - speed cr r un mode cpu/ peripheral: 4 mhz* 2 main flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 5 17 ma *1 sub r un mode cpu/ peripheral: 32 khz main flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 1.3 14 ma *1 , *6 low - speed cr r un mode cpu/ peripheral: 100 khz main flash 0 wait frwtr.rwt = 00 fsyndn.sd = 000 1.3 14 ma *1 sleep mode current i ccs pll s leep mode peripheral: 72 mhz 28 43 ma *1 , *5 high - speed cr s leep mode peripheral: 4 mhz* 2 3 16 ma *1 sub s leep mode peripheral: 32 khz 1 14 ma *1 , *6 low - speed cr s leep mode peripheral: 100 khz 1 14 ma *1 *1: when all ports are fixed. *2: when setting it to 4 mhz by trimming. *3: t a =+25c, v cc =5.5 v *4: t a =+85c, v cc =5.5 v *5: when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit) *6: when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circ uit)
document number: 002 - 08541 rev.*c page 65 of 117 mb9b510r s eries parameter symbol pin name conditions value unit remarks typ * 2 max * 2 t imer mode current i cct v cc main t imer mode t a = + 25 c , when lvd is off 3.2 6 ma *1 , *3 t a = + 85 c , when lvd is off - 15 ma *1 , *3 sub t imer mode t a = + 25 c , when lvd is off 0.9 3 ma *1 , *4 t a = + 85 c , when lvd is off - 12 ma *1 , *4 s top mode current i cch s top mode t a = + 25 c , when lvd is off 0.8 3 ma *1 t a = + 85 c , when lvd is off - 12 ma *1 *1: when all ports are fixed. *2: v cc =5.5 v *3: when using the crystal oscillator of 4 mhz(including the current consumption of the oscillation circuit) *4: when using the crystal oscillator of 32 khz(including the current consumption of the oscillation circuit) low - voltage detection current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks typ max low voltage detection circuit (lvd) power supply current i cclvd vcc at operation for interrupt v cc = 5.5 v 4 7 a flash memory current (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks typ max flash m emory w rite/ e rase current i ccflash vcc mainflash at write/erase 11.4 13.1 ma * workflash at write/erase 11.4 13.1 ma *: the current at which to write or erase flash memory, i ccflash is added to i cc . a/d converter current (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks typ max power supply current i ccad avcc at 1unit operation 0.47 0.62 ma at stop 0.06 25 ccavrh avrh at 1unit operation avrh=5.5 v 1.1 1.96 ma at stop 0.06 4
document number: 002 - 08541 rev.*c page 66 of 117 mb9b510r s eries 12.3.2 pin characteristics (v cc = usbv cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min typ max h level input voltage (hysteresis input) v ihs cmos hysteresis input pin , md0 , md1 - v cc 0.8 - v cc + 0.3 v 5 v tolerant input pin - v cc 0.8 - v ss + 5.5 v l level input voltage (hysteresis input) v ils cmos hysteresis input pin , md0 , md1 - v ss - 0.3 - v cc 0.2 v 5 v tolerant input pin - v ss - 0.3 - v cc 0.2 v h level output voltage v oh 4 ma type v cc oh = - 4 ma v cc - 0.5 - v cc v v cc < 4.5 v i oh = - 2 ma 12 ma type v cc oh = - 12 ma v cc - 0.5 - v cc v v cc < 4.5 v i oh = - 8 ma p80, p81 usb v cc oh = - 20.5 ma usbv cc - 0.4 - usbv cc v usb v cc < 4.5 v i oh = - 13.0 ma
document number: 002 - 08541 rev.*c page 67 of 117 mb9b510r s eries parameter symbol pin name conditions value unit remarks min typ max l level output voltage v ol 4 ma type v cc 4.5 v i ol = 4 ma v ss - 0.4 v v cc < 4.5 v i ol = 2 ma 12 ma type v cc 4.5 v i ol = 12 ma v ss - 0.4 v v cc < 4.5 v i ol = 8 ma p80, p81 usb v cc 4.5 v i ol = 18.5 ma v ss - 0.4 v usb v cc < 4.5 v i ol = 10.5 ma input leak current i il - - - 5 - + 5 a pull - up resistance value r pu pull - up pin v cc 4.5 v 25 50 100 k v cc < 4.5 v 30 80 200 input capacitance c in other than vcc, usbvcc, vss, avcc, avss, avrh - - 5 15 pf
document number: 002 - 08541 rev.*c page 68 of 117 mb9b510r s eries 12.4 ac characteristics 12.4.1 main clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0 x1 v cc cc < 4.5 v 4 20 v cc cc < 4.5 v 4 20 input clock cycle t cylh v cc cc < 4.5 v 50 250 input clock pulse width - p wh /t cylh p wl /t cylh 45 55 % when using external clock input clock rise time and fall time t cf , t cr - - 5 ns when using external clock internal operating c lock * 1 frequency f cm - - - 144 mhz master clock f cc - - - 144 mhz base clock (hclk/fclk) f cp0 - - - 72 mhz apb0 bus clock * 2 f cp1 - - - 72 mhz apb1 bus clock * 2 f cp 2 - - - 72 mhz apb2 bus clock * 2 internal operating clock * 1 cycle time t cycc - - 6.94 - ns base clock (hclk/fclk) t cycp0 - - 13.8 - ns apb0 bus clock * 2 t cycp1 - - 13.8 - ns apb1 bus clock * 2 t cycp2 - - 13.8 - ns apb2 bus clock * 2 *1: for more information about each internal operating clock, see chapter 2 - 1: clock in fm3 family peripheral manual. *2: for about each apb bus which each peripheral is connected to, see 8 block diagram in this data sheet. x0
document number: 002 - 08541 rev.*c page 69 of 117 mb9b510r s eries 12.4.2 sub clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min typ max input frequency 1/ t cyll x0a x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 wh /t cyll p wl /t cyll 45 - 55 % when using external clock 12.4.3 i nternal cr oscillation characteristics high - speed internal cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c 3.9 6 4 4.0 4 mhz when trimming * 1 t a = 0 c to + 70 c 3.84 4 4.16 t a = - 40 c to + 85 c 3.8 4 4.2 t a = - 40 c to + 85 c 3 4 5 when not trimming f requency stability time t crwt - - - 90 low - speed internal cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 k hz x0a
document number: 002 - 08541 rev.*c page 70 of 117 mb9b510r s eries 12.4.4 operating conditions of main and usb pll (in the case of using main clock for input of pll) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 4 - 16 mh z pll multiple rate - 13 - 75 multiple pll macro oscillation clock frequency f pllo 200 - 300 mh z main pll clock frequency* 2 f clkpll - - 144 mh z usb clock frequency* 3 f clkspll - - 48 mh z after the m frequency division *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see chapter 2 - 1: clock in fm3 family peripheral manual. *3: for more information about usb clock, see chapter 2 - 2: usb clock generation in fm3 family peripheral manual communication macro part. 12.4.5 operating conditions of main pll (in the case of using high - speed internal cr) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - plli 3.8 4 4.2 mh z pll multiple rate - 50 - 71 multiple pll macro oscillation clock frequency f pllo 190 - 300 mh z main pll clock frequency* 2 f clkpll - - 144 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see chapter 2 - 1: clock in fm3 family peripheral manual. when setting pll multiple rate, please take the accuracy of the built - in high - speed cr clock into account and prevent the master clock from exceeding the maximum frequency. main clock (clkmo) k divider pll input clock usb pll m divider usb clock n divider usb pll connection pll macro oscillation clock k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection high - speed cr clock (clkhc) main clock (clkmo)
document number: 002 - 08541 rev.*c page 71 of 117 mb9b510r s eries 12.4.6 reset input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - ns 12.4.7 power - on reset timing (v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min typ max power supply shut down time t off vcc - 50 - - ms *1 power ramp rate dv/dt vcc: 0.2 v to 2.70 v 0.8 - 1000 mv/ prt - 0.57 - 0.76 ms *1: v cc must be held below 0.2 v for minimum period of t off . improper initialization may occur if this condition is not met. *2: this dv/dt characteristic is applied at the power - on of cold start (t off >50 ms). note: ? if t off cannot be satisfied designs must assert external reset(initx) at power - up and at any brownout event per 1 2 . 4. 6 . reset input characteristics . glossary vdh: detection voltage of low voltage detection reset. s ee 12.7. low - voltage detection characteristics v d h t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e 0 . 2 v 0 . 2 v t o f f d v / d t 0 . 2 v 2 . 7 v
document number: 002 - 08541 rev.*c page 72 of 117 mb9b510r s eries 12.4.8 external bus timing external bus clock output characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit min max out put frequency t cycle mclkout * 1 v cc 2 mhz v cc < 4.5 v - 32 * 3 mhz *1: external bus clock (mclkout) is divided clock of hclk. for more information about setting of clock divider, see chpater 12: external bus interface in fm3 family peripheral manual. when external bus clock is not output, this characteristic does not give any effect on external bus operation. *2: when ahb bus clock frequency is more than 100mhz, the divider setting for mclkout must be more than 4. *3: when ahb bus clock frequency is more than 64mhz, the divider setting for mclkout must be more than 4. external bus signal input/output characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol conditions value unit remarks signal input c haracteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output c haracteristics v oh 0.8 v cc v v ol 0.2 v cc v mclkout input signal output signal v ih v il v il v ih v oh v ol v ol v oh
document number: 002 - 08541 rev.*c page 73 of 117 mb9b510r s eries separate bus access asynchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit min max moex min pulse width t oew moex v cc mclk n - 3 - ns v cc < 4.5 v mcsx csl C av mcsx[7:0] mad[24:0] v cc - 9 + 9 ns v cc < 4.5 v - 12 + 12 moex oeh - ax moex mad[24:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx cs l - oe l moex mcsx[7:0] v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 moex oeh - c sh v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx cs l - r dqml mcsx mdqm[1:0] v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 data set up ds - oe moex madata[15:0] v cc 20 - ns v cc < 4.5 v 38 - moex dh - oe moex madata[15:0] v cc 0 - ns v cc < 4.5 v m wex min pulse width t wew mwex v cc mclk n - 3 - ns v cc < 4.5 v mwex weh - ax mwex mad[24:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx csl - wel mwex mcsx[7:0] v cc mclk n - 9 mclk n+9 ns v cc < 4.5 v mclk n - 12 mclk n+12 mwex weh - csh v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx cs l - w dqml mcsx mdqm[1:0] v cc mclk n - 9 mclk n+9 ns v cc < 4.5 v mclk n - 12 mclk n+12 mcsx cs l - dv mcsx madata[15:0] v cc - 9 mclk + 9 ns v cc < 4.5 v mclk - 12 mclk + 12 mwex weh - dx mwex madata[15:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 note : ? when the external load capacitance = 30 pf. (m = 0 to 15, n = 1 to 16)
document number: 002 - 08541 rev.*c page 74 of 117 mb9b510r s eries mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d a d d r e s s t c s l - o e l t c s l - a v r d a d d r e s s w d t d h - o e t d s - o e t w e h - d x t o e w t o e h - a x t o e h - c s h t w e w t c y c l e t c s l - w e l t c s l - a v t w e h - c s h t w e h - a x t c s l - w d q m l t c s l - r d q m l t c s l - d v
document number: 002 - 08541 rev.*c page 75 of 117 mb9b510r s eries separate bus access synchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit min max address delay time t av mclk mad[24:0] v cc cc < 4.5 v 12 mcsx delay time t csl mclk mcsx[7:0] v cc cc < 4.5 v 12 t cs h v cc cc < 4.5 v 12 moex delay time t rel mclk moex v cc cc < 4.5 v 12 t reh v cc cc < 4.5 v 12 data set up ds mclk madata[15:0] v cc - ns v cc < 4.5 v 37 mclk dh mclk madata[15:0] v cc - ns v cc < 4.5 v mwex delay time t wel mclk mwex v cc cc < 4.5 v 12 t we h v cc cc < 4.5 v 12 mdqm[1:0] delay time t dqml mclk mdqm[1:0] v cc cc < 4.5 v 12 t dqmh v cc cc < 4.5 v 12 mclk ods mclk, madata[15:0] v cc cc < 4.5 v mclk+24 mclk od mclk madata[15:0] v cc cc < 4.5 v 24 note : ? when the external load capacitance = 30 pf. mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s
document number: 002 - 08541 rev.*c page 76 of 117 mb9b510r s eries multiplexed bus access asynchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit min max multiplexed a ddress delay time t a le - chmadv male madata[15:0] v cc cc < 4.5 v 20 multiplexed a ddress hold time t c hmadh v cc cc < 4.5 v mclk n+0 mclk n+20 note : ? when the external load capacitance = 30 pf. (m = 0 to 15, n = 1 to 16) mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 08541 rev.*c page 77 of 117 mb9b510r s eries multiplexed bus access synchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk ale v cc cc < 4.5 v 1 2 ns t chah v cc cc < 4.5 v 12 ns mclk chmadv m clk madata[15:0] v cc od ns v cc < 4.5 v mclk chmad x v cc od ns v cc < 4.5 v note : ? when the external load capacitance = 30 pf. mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 08541 rev.*c page 78 of 117 mb9b510r s eries nand flash mode (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to +85c) parameter symbol pin name conditions value unit min max m nrex min pulse width t nrew mnrex v cc mclk n - 3 - ns v cc < 4.5 v data setup ds C nre mnrex madata[15:0] v cc 20 - ns v cc < 4.5 v 38 - mnrex dh C nre mnrex madata[15:0] v cc 0 - ns v cc < 4.5 v mnale aleh - nwel mnale mnwex v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 mnale ale l - nwel mnale mnwex v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 mncle cleh - nwel mncle mnwex v cc mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 mnwex nweh - clel mncle mnwex v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mnwex min pulse width t nwew mnwex v cc mclk n - 3 - ns v cc < 4.5 v mnwex nwel C dv mnwex madata[15:0] v cc - 9 + 9 ns v cc < 4.5 v - 12 +12 mnwex nweh C dx mnwex madata[15:0] v cc 0 mclk m+9 ns v cc < 4.5 v mclk m+12 note : ? when the external load capacitance = 30 pf. (m=0 to 15, n=1 to 16) nand f lash read mcl k mnrex madata [ 15 : 0 ] read
document number: 002 - 08541 rev.*c page 79 of 117 mb9b510r s eries nand flash address write nand flash command write mclk mnale mncle mnwex write mcl k mna l e mnc l e madata [ 15 : 0 ] mnw e x write madata [ 15 : 0 ]
document number: 002 - 08541 rev.*c page 80 of 117 mb9b510r s eries external ready input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max mclk rdyi mclk mrdy v cc cc < 4.5 v 37 when rdy is input when rdy is released mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycle t rdyi 2 cycle t rdyi 0.5vcc
document number: 002 - 08541 rev.*c page 81 of 117 mb9b510r s eries 12.4.9 base timer input timing timer input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh t tiwl tioan/tiobn (when using as eck , tin) - 2 t cycp - ns trigger input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note : ? t cycp indicates the apb bus clock cycle time. about the apb bus number which base timer is connected to, see 8 block diagram in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 08541 rev.*c page 82 of 117 mb9b510r s eries 12.4.10 csio/uart timing csio (spi = 0, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sck x master mode 4 t cycp - 4 t cycp - ns sck slovi sckx sotx - 30 +30 - 20 + 20 ns sin ivshi sckx sinx 50 - 30 - ns sck shixi sckx sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck slove sckx sotx - 50 - 30 ns sin ivshe sckx sinx 10 - 10 - ns sck shixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes : ? ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected t o , see 8 block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf.
document number: 002 - 08541 rev.*c page 83 of 117 mb9b510r s eries master mode slave mode t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi sck sot sin t slsh t shsl v ih t f t r v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe sck sot sin
document number: 002 - 08541 rev.*c page 84 of 117 mb9b510r s eries csio (spi = 0, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck shovi sckx sotx - 30 +30 - 20 + 20 ns sin ivsli sckx sinx 50 - 30 - ns sck slixi sckx sinx 0 - 0 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck shove sckx sotx - 50 - 30 ns sin ivsle sckx sinx 10 - 10 - ns sck slixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes : ? ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to, see 8 block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf.
document number: 002 - 08541 rev.*c page 85 of 117 mb9b510r s eries master mode slave mode t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi sck sot sin t shsl t slsh v ih t f t r v ih v oh v il v il v il v ol v ih v il v ih v il t ivsle t slixe sck sot sin t shove
document number: 002 - 08541 rev.*c page 86 of 117 mb9b510r s eries csio (spi = 1, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck shovi sckx sotx - 30 +30 - 20 + 20 ns sin ivsli sckx sinx 50 - 30 - ns sck slixi sckx sinx 0 - 0 - ns sot sovli sckx sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck shove sckx s ot x - 50 - 30 ns sin ivsle sckx sinx 10 - 10 - ns sck slixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes : ? ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to, see 8 block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number . for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf.
document number: 002 - 08541 rev.*c page 87 of 117 mb9b510r s eries master mode slave mode *: changes when writing to tdr register t sovli t scyc t shovi v ol v ol v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivsli t slixi sck sot sin t f t r t slsh t shsl t shove v i l v i l v ih v ih v ih v oh * v o l v oh v o l v ih v i l v ih v i l t ivsle t slixe sck sot sin
document number: 002 - 08541 rev.*c page 88 of 117 mb9b510r s eries csio (spi = 1, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4 t cycp - 4 t cycp - ns sck slovi sckx sotx - 30 +30 - 20 + 20 ns sin ivshi sckx sinx 50 - 30 - ns sck shixi sckx sinx 0 - 0 - ns sot sovhi sckx sotx 2 t cycp - 30 - 2 t cycp - 30 - ns serial clock l pulse width t slsh sckx slave mode 2 t cycp - 10 - 2 t cycp - 10 - ns serial clock h pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck slove sckx s ot x - 50 - 30 ns sin ivshe sckx sinx 10 - 10 - ns sck shixe sckx sinx 20 - 20 - ns sck fall time t f sckx - 5 - 5 ns sck rise time t r sckx - 5 - 5 ns notes : ? ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which multi - function serial is connected to, see 8 block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? w hen the external load capacitance = 30 pf.
document number: 002 - 08541 rev.*c page 89 of 117 mb9b510r s eries master mode slave mode uart e xternal clock input (ext = 1 ) ( v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 85 c ) parameter symbol conditions min max unit remarks serial clock l pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock h pulse width t shsl t cycp + 10 - ns sck fall time t f - 5 ns sck rise time t r - 5 ns t scyc t slovi v ol v oh v oh v oh v o l v oh v o l v ih v i l v ih v i l t ivshi t shixi t sovhi sck sot sin t shsl t r t slsh t f t slove v il v il v il v ih v ih v oh v o l v oh v o l v ih v il v ih v il t ivshe t shixe sck sot sin t shsl v i l v i l v i l v ih v ih t r t f t slsh s ck
document number: 002 - 08541 rev.*c page 90 of 117 mb9b510r s eries 12.4.11 external input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max input pulse width t inh , t inl adtg - 2 t cycp * - ns a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * - ns wave form generator int xx, nmix except timer mode, stop mode 2 t cycp + 100 * - ns external interrupt nmi timer mode, stop mode 500 * 2 - ns *: t cycp indicates the apb bus clock cycle time. about the apb bus number which a/d converter, multi - function timer, external interrupt is connected to, see 8 block diagram in this data sheet.
document number: 002 - 08541 rev.*c page 91 of 117 mb9b510r s eries 12.4.12 quadrature position/revolution counter timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol conditions value unit min max ain pin h width t ahl - 2 t cycp * - ns ain pin l width t all - bin pin h width t bhl - bin pin l width t bll - bin rise time from ain pin h level t aubu pc_mode2 or pc_ m ode3 ain fall time from bin pin h level t buad pc_mode2 or pc_mode3 bin fall time from ain pin l level t adbd pc_mode2 or pc_mode3 ain rise time from bin pin l level t bdau pc_mode2 or pc_mode3 ain rise time from bin pin h level t buau pc_mode2 or pc_mode3 bin fall time from ain pin h level t aubd pc_mode2 or pc_mode3 ain fall time from bin pin l level t bdad pc_mode2 or pc_mode3 bin rise time from ain pin l level t adbu pc_mode2 or pc_mode3 zin pin h width t zhl qcr:cgsc=0 zin pin l width t zll qcr:cgsc=0 ain/bin rise and fall time from determined zin level t zabe qcr:cgsc=1 determined zin level from ain/bin rise and fall time t abez qcr:cgsc=1 * : t cycp indicates the apb bus clock cycle time. about the apb bus number which quadrature position/revolution counter is connected to, see 8 block diagram in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll
document number: 002 - 08541 rev.*c page 92 of 117 mb9b510r s eries zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 08541 rev.*c page 93 of 117 mb9b510r s eries 12.4.13 i 2 c timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol conditions standard - mode fast - mode unit remarks min max min max scl clock frequency f scl c l = 30 pf, r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda hdsta 4.0 - 0.6 - low 4.7 - 1.3 - high 4.0 - 0.6 - susta 4.7 - 0.6 - hddat 0 3.45* 2 0 0.9* 3 sudat 250 - 100 - ns stop condition setup time scl susto 4.0 - 0.6 - buf 4.7 - 1.3 - sp 8 mhz cycp cycp * 4 - 2 t cycp * 4 - ns *5 40 mhz < t cycp cycp * 4 - 3 t cycp * 4 - ns *5 60 mhz < t cycp cycp * 4 - 4 t cycp * 4 - ns *5 *1: r and c represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2: the maximum t hddat must satisfy that it doesn't extend at least l period (t low ) of device's scl signal. *3: fast - mode i 2 c bus device can be used on standard - mode i2c bus system as long as the device satisfies the requirement of t sudat 250 ns. *4: t cycp is the apb bus cloc k cycle time. about the apb bus number that i 2 c is connected to, see 8 block diagram in this data sheet. to use standard - mode, set the apb bus clock at 2 mhz or more. to use fast - mode, set the apb bus clock at 8 mhz or more. *5: the number of the steps of the noise filter can be changed by register settings. change the number of the noise filter steps according to apb2 bus clock frequency. sda s cl
document number: 002 - 08541 rev.*c page 94 of 117 mb9b510r s eries 12.4.14 etm timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk traced [ 3 : 0 ] v cc 4.5 cc < 4.5 v 2 15 traceclk frequency 1/ t trace traceclk v cc 4.5 cc < 4.5 v - 32 mhz traceclk cycle time t trace v cc 4.5 cc < 4.5 v 31.25 - ns note : ? when the external load capacitance = 30 pf. hclk traceclk traced[3:0]
document number: 002 - 08541 rev.*c page 95 of 117 mb9b510r s eries 12.4.15 jtag timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks min max tms , tdi setup time t jtags tck , tms , tdi v cc cc < 4.5 v tms , tdi hold time t jtagh tck , tms , tdi v cc cc < 4.5 v tdo delay time t jtagd tck , tdo v cc cc < 4.5 v - 45 note : ? when the external load capacitance = 30 pf. tck tms/ tdi tdo
document number: 002 - 08541 rev.*c page 96 of 117 mb9b510r s eries 12.5 12 - bit a/d converter electrical characteristics for the a/d converter (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 85c) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 4.0 4.5 lsb avrh = 2.7 v to 5.5 v differential nonlinearity - - - 2.3 2.5 lsb zero transition voltage v z t an xx - 10 15 mv full - scale transition voltage v fst an xx - avrh 10 avrh 15 mv conversion time - - 1.0* 1 - - cc 1 - - av cc < 4.5 v sampling time t s - *2 - - ns av cc cc < 4.5 v compare clock cycle* 3 t cck - 50 - 2000 ns av cc cc < 4.5 v state transition time to operation permission t stt - - - 1.0 ain - - - 12.9 pf analog input resistance r ain - - - 2 k cc cc < 4.5 v interchannel disparity - - - - 4 lsb analog port input leak current - an xx - - 5 ss - avrh v reference voltage - avrh 2.7 - av cc v *1: conversion time is the value of sampling time (t s ) + compare time (t c ). the condition of the minimum conversion time is the following. av cc 4.5 v, hclk=120 hz sampling time: 300 ns, compare time: 700 ns av cc < 4.5 v, hclk=120 hz sampling time: 500 ns, compare time: 700 ns ensure that it satisfies the value of sampling time (t s ) and compare clock cycle (t cck ). for setting*4 of sampling time and compare clock cycle, see chapter 1 - 1: 12 - bit a/d converter in fm3 family peripheral manual analog macro part. a/d converter register is set at apb bus clock timing. sampling and compare clock is set at base clock (hclk). about the apb bus number which the a/d converter is connected to, see 8 block diagram in th is data sheet. *2: a necessary sampling time changes by external impedance. ensure that it set the sampling time to satisfy (equation 1). *3: compare time (tc) is the value of (equation 2).
document number: 002 - 08541 rev.*c page 97 of 117 mb9b510r s eries (equation 1) t s ( r ain + r ext ) c ain 9 t s : sampling time r ain : i nput resistance of a/d = 2 k at 4.5 v < av cc < 5.5 v i nput resistance of a/d = 3.8 k at 2.7 v < av cc < 4.5 v c ain : i nput capacity of a/d = 12.9 pf at 2.7 v < av cc < 5.5 v r ext : output impedance of external circuit (equation 2) t c = t cck 14 t c : compare time t cck : compare clock cycle r ext r ain c ain analog signal source an xx analog input pin c omparator
document number: 002 - 08541 rev.*c page 98 of 117 mb9b510r s eries definition of 12 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonlinearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential nonlinearity: deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v zt } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v z t 4094 n: a/d converter digital output value. v zt : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff av ss avrh av ss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 08541 rev.*c page 99 of 117 mb9b510r s eries 12.6 usb characteristics (v cc = 2.7v to 5.5v, usbv cc = 3.0v to 3.6v, v ss = 0v, t a = - 40c to + 85c) parameter symbol pin name conditions value unit remarks m in m ax input charact - eristics input h level voltage v ih udp0, udm0 - 2.0 usbv cc + 0.3 v *1 input l level voltage v il - v ss - 0.3 0.8 v *1 differential input sensitivity v di - 0.2 - v *2 different common mode input voltage v cm - 0.8 2.5 v *2 output charact - erstics output h level voltage v oh external pull - down resistance = 15 k ol external pull - up resistance = 1.5 k crs - 1.3 2.0 v *4 rise time t fr full - speed 4 20 ns *5 fall time t ff full - speed 4 20 ns *5 rise/ fall time matching t frfm full - speed 90 111.11 % *5 output impedance z drv full - speed 28 44 lr low - speed 75 300 ns *7 fall time t lf low - speed 75 300 ns *7 rise/ fall time matching t lrfm low - speed 80 125 % *7 *1: the switching threshold voltage of single - end - receiver of usb i/o buffer is set as within v il (max) = 0.8 v, v ih (min) = 2.0 v (ttl input standard). there are some hystereses to lower noise sensitivity. *2: use differential - receiver to receive usb differential data signal. differential - receiver has 200 mv of differential input sensitivity when the differential data input is within 0.8 v to 2.5 v to the local ground reference level. above voltage range is the common mode input voltage range. common mode input voltage [v] minimum differential input sensitivity [v]
document number: 002 - 08541 rev.*c page 100 of 117 mb9b510r s eries *3: the output drive capability of the driver is below 0.3 v at low - state (v ol ) (to 3.6 v and 1.5 k load), and 2.8 v or above (to the vss and 1.5 k load) at high - state (v oh ). *4: the cross voltage of the external differential output signal (d + /d ?he of usb i/o buffer is within 1.3 v to 2.0 v. *5: they indicate rise time (trise) and fall ti me (tfall) of the full - speed differential data signal. they are defined by the time between 10% and 90 % of the output signal voltage. for full - speed buffer, tr/tf ratio is regulated as within 10 % to mini mize rfi emission. v crs specified range rising time falling time
document number: 002 - 08541 rev.*c page 101 of 117 mb9b510r s eries *6: usb full - speed connection is performed via twist pair cable shield with 90 15% characteristic impedance (differential mode). usb standard defines that output impedance of usb driver must be in range from 28 to 44 . so, discrete series resistor (rs) addition is defined in order to satisfy the above definition and keep balance. when using this usb i/o, use it with 25 to 30 (recommendation value 27 ) series resistor rs. rs series resistor 25 to 30 series resistor of 27 (recommendation value) must be added. and, use resistance with an uncertainty of 5% by e24 sequence. *7: they indicate rise time (trise) and fall time (tfall) of the low - speed differential data signal. they are defined by the time between 10 % and 90 % of the output signal voltage. see figure ? low - speed load (compliance load) for conditions of external load. mount it as external resistance. 28 to 44 equiv. imped. 28 to 44 equiv. imped. rising time falling time
document number: 002 - 08541 rev.*c page 102 of 117 mb9b510r s eries low - speed load (upstream port load) - reference 1 low - speed load (downstream port load) - reference 2 low - speed load (compliance load) c l = 50pf to 150pf c l = 50pf to 150pf c l =200pf to 600pf c l =200pf to 600pf c l = 200pf to 450pf c l = 200pf to 450pf
document number: 002 - 08541 rev.*c page 103 of 117 mb9b510r s eries 12.7 low - voltage detection characteristics 12.7.1 low - voltage detection reset ( t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl - 2.25 2.45 2.65 v when voltage drops released voltage vdh - 2.30 2.50 2.70 v when voltage rises 12.7.2 interrupt of low - voltage detection ( t a = - 40 c to + 85 c ) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 0000 2.58 2.8 3.02 v when voltage drops released voltage vdh 2.67 2.9 3.13 v when voltage rises detected voltage vdl svhi = 0001 2.76 3.0 3.24 v when voltage drops released voltage vdh 2.85 3.1 3.34 v when voltage rises detected voltage vdl svhi = 0010 2.94 3.2 3.45 v when voltage drops released voltage vdh 3.04 3.3 3.56 v when voltage rises detected voltage vdl svhi = 0011 3.31 3.6 3.88 v when voltage drops released voltage vdh 3.40 3.7 3.99 v when voltage rises detected voltage vdl svhi = 0100 3.40 3.7 3.99 v when voltage drops released voltage vdh 3.50 3.8 4.10 v when voltage rises detected voltage vdl svhi = 0111 3.68 4.0 4.32 v when voltage drops released voltage vdh 3.77 4.1 4.42 v when voltage rises detected voltage vdl svhi = 1000 3.77 4.1 4.42 v when voltage drops released voltage vdh 3.86 4.2 4.53 v when voltage rises detected voltage vdl svhi = 1001 3.86 4.2 4. 53 v when voltage drops released voltage vdh 3.96 4.3 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 4032 t cycp * cycp indicates the apb2 bus clock cycle time.
document number: 002 - 08541 rev.*c page 104 of 117 mb9b510r s eries 12.8 mainflash memory write/erase characteristics 12.8.1 write / erase time (v cc = 2.7v to 5.5v, t a = - 40c to + 85c) parameter value unit remarks typ* max* sector erase time large sector 0. 7 3.7 s includ es write time prior to internal erase small sector 0.3 1.1 half word (16 - bit) write time 12 384 12.8.2 erase/write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1 , 000 20* 10 , 000 10* 100 , 000 5* * : at average + 85 ? c 12.9 workflash memory write/erase characteristics 12.9.1 write / erase time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 85 c ) parameter value unit remarks typ* max* sector erase time 0.3 1.5 s includ es write time prior to internal erase half word (16 - bit) write time 20 384 12.9.2 erase/write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1 , 000 20* 10 , 000 10* *: at average + 85 ? c
document number: 002 - 08541 rev.*c page 105 of 117 mb9b510r s eries 12.10 return time from low - power consumption mode 12.10.1 return factor: interrupt the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. return count time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 8 5 c ) parameter symbol value unit remarks typ max* s leep mode t icnt t cycc ns high - speed cr t imer mode, main t imer mode, pll t imer mode 40 80 operation example of return from low - power consumption mode (by external interrupt*) * : external interrupt is set to detecting fall edge. e x t e r n a l i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 08541 rev.*c page 106 of 117 mb9b510r s eries operation example of return from low - power consumption mode (by internal resource interrupt*) * : internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes : ? the return factor is different in each low - power consumption modes. see " c hapter 6 : low power consumption mode and operations of standby modes " in " fm3 family peripheral manual " about the return factor from l ow - p ower consumption mode. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state b efore the low - power consumption mode transition. see "chapter 6: low power consumption mode" in "fm3 family peripheral manual". i n t e r n a l r e s o u r c e i n t e r r u p t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 08541 rev.*c page 107 of 117 mb9b510r s eries 12.10.2 return factor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. return count time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 8 5 c ) parameter symbol value unit remarks typ max* s leep mode t rcnt 321 461 operation example of return from low - power consumption mode (by initx) i n i t x t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e
document number: 002 - 08541 rev.*c page 108 of 117 mb9b510r s eries operation example of return from low power consumption mode (by internal resource reset*) * : internal resource reset is not included in return factor by the kind of low - power consumption mode. notes : ? the return factor is different in each low - power consumption modes. see "chapter 6: low power consumption mode and operations of standby modes" in "fm3 family peripheral manual." ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transition. see "chapter 6: low power consumption mode" in "fm3 family peripheral manual". ? the time during the power - on reset/low - voltage detection reset is excluded. see "(6) power - on reset timing" in "4. ac characteristics" i n " 12 electrical characteristics " for the detail on the time during the po wer - on reset/low - voltage detection reset. ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r e s e t t r c n t i n t e r n a l r e s e t c p u o p e r a t i o n s t a r t r e s e t a c t i v e r e l e a s e
document number: 002 - 08541 rev.*c page 109 of 117 mb9b510r s eries 13. ordering information part number on - chip flash memory on - chip sram package packing mb9bf 5 1 2np qc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte plastic ? qfp 1 00 - pin (0. 6 5 mm pitch) , ( pqh100 ) tray mb9bf 5 1 4np qc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 5 15np qc - g - jne2 main: 384 kbyte work: 32 kbyte 48 kbyte mb9bf 5 1 6np qc - g - jne2 main: 512 kbyte work: 32 kbyte 64 kbyte mb9bf 5 1 2npmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp 1 00 - pin (0.5 mm pitch) , ( lqi100 ) mb9bf 5 1 4npmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 5 15npmc - g - jne2 main: 384 kbyte work: 32 kbyte 48 kbyte mb9bf 5 1 6npmc - g - jne2 main: 512 kbyte work: 32 kbyte 64 kbyte mb9bf 5 1 2rpmc - g - jne2 main: 128 kbyte work: 32 kbyte 16 kbyte plastic ? lqfp 1 20 - pin (0. 5 mm pitch) , ( lqm120 ) mb9bf 5 1 4rpmc - g - jne2 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 5 15rpmc - g - jne2 main: 384 kbyte work: 32 kbyte 48 kbyte mb9bf 5 1 6rpmc - g - jne2 main: 512 kbyte work: 32 kbyte 64 kbyte mb9bf 5 12nbgl - ge1 main: 128 kbyte work: 32 kbyte 16 kbyte plastic ? fbga 1 12 - pin (0. 8 mm pitch) , ( lbc112 ) mb9bf 5 14nbgl - ge1 main: 256 kbyte work: 32 kbyte 32 kbyte mb9bf 5 15nbgl - ge1 main: 384 kbyte work: 32 kbyte 48 kbyte mb9bf 5 16nbgl - ge1 main: 512 kbyte work: 32 kbyte 64 kbyte
document number: 002 - 08541 rev.*c page 110 of 117 mb9b510r s eries 14. package dimensions package type package code lqfp 100 lqi100 0 02 - 11500 * a n o t e s : 1 . a ll d i m e n s io n s a r e i n m i ll i m e t e r s . 2. d a t u m pla n e h i s lo c a t e d a t t h e bot t o m of t h e mold partin g li n e coi n c i d e n t w i t h w h e r e t h e l e a d e x i t s t h e body . 3 . d a tums a - b a n d d t o b e d e t e rmi n e d a t d a t u m p l a n e h . 4. to b e d e t e r m i n e d a t s e a t i n g plane c . 5 . d i m e n sio n s d1 a nd e 1 d o n ot i nc l ud e m ol d p r o t ru si o n . allowable protrusi o n is 0 . 25 mm p r e si d e . d i m e n s i o n s d 1 a n d e 1 i n c l u d e m o l d m i s m a t c h a n d a r e d e t e rmine d a t d a t u m plane h . 6 . d e t a i l s o f p i n 1 i d e n t i f i e r a r e o p t i o n a l b u t m u s t be l o c ate d w i t h i n th e zo n e i n d i c a t e d . 7 . r e g a r d l e s s of t h e r e l a t i v e s i z e o f t h e u p p e r a n d l o w e r b o d y s e c t i o n s . d i m e n s i o n s d 1 a n d e 1 a r e d e t e r m i n e d a t t h e larges t f e a t u r e o f t h e b o d y e x c l u s i v e o f m o l d f l a s h a n d g a te burrs . b u t i n clu d i n g a n y m i s m a t c h b e t w e e n t h e u p p e r a nd lowe r s e c t ion s of t h e mol d e r b o dy . 8 . d i m e n s i o n b d o e s n o t i n c l u d e d a m b a r p r o t r u s i o n . t h e d a mba r p r o t r u s i o n ( s ) s h a l l n o t c a u s e t h e l e a d w i d t h to e x c e e d b m a x i m u m b y m o r e t h a n 0 . 0 8 m m . d a m b a r c a n n o t b e l o cated o n t h e l o w e r r a d i u s o r t h e l e a d f oot . 9. t h e s e d i m e n s ion s a p p l y t o t h e fla t s e c t i o n of the lea d b e t w e e n 0 . 10m m a n d 0.25 m m f r o m t h e lead tip . 10 . a 1 i s d e f i n e d a s t h e d i s t a n c e f r om t h e s e a t i n g p l a n e t o t h e low e s t p o i n t of t h e p a c k age body . d im e n s io n s symbol m in . n o m . max . a 1.7 0 a1 0.0 5 0.1 5 b 0 .1 5 0 .2 7 c 0 .0 9 0 .2 0 d 1 6 . 00 bsc d 1 1 4 .00 bs c e 0 . 50 bsc e e1 l 0 .4 5 0 .6 0 0 .7 5 l1 0.3 0 0.5 0 0.7 0 1 6. 00 bsc 1 4. 00 bsc a a 1 0.25 0.0 8 c 1 100 d 1 d e 1 e e 4 4 0.0 8 c a - b d 7 5 seat i n g pla n e 0.2 0 c a - b d 0.1 0 c a - b d b se c t io n a-a ' c 9 a a ' 5 7 5 7 3 3 6 8 1 0 2 2 l1 l b d 1 d e 1 e 4 4 5 7 5 7 25 26 50 51 75 76 side v i ew top v i ew b o tt o m vie w d e t a il a 1 25 26 50 5 7 1 5 100 76 package ou t line, 1 00 le a d l q f p 14.0x14.0x1.7 mm lq i 100 r ev * a
document number: 002 - 08541 rev.*c page 111 of 117 mb9b510r s eries package type package code lqfp 120 lqm120 0 02 - 16172 ** m i n . n o m . m ax . 0 7 . 1 a a 1 0 . 0 5 0 . 1 5 b 0 .1 7 0 .2 2 0 .2 7 c 0 . 1 1 5 0 . 1 9 5 d 1 8 . 0 0 b s c d 1 1 6 . 0 0 b s c e 0 . 5 0 bs c e e 1 l 0 .4 5 0 .6 0 0 .7 5 1 8 . 0 0 b s c 1 6 . 0 0 b s c d i m e n s io n s s y m b o l 0 8 s i d e vie w b o tt o m vie w t o p v i e w 1 120 d 1 d e e e 1 0.20 c a - b d 0.10 c a - b d 0.08 c a - b d b 0.08 c s eati n g pla n e a a' a a 1 0.25 1 0 l b s ec t i on a - a' c 9 4 5 7 3 4 5 7 3 8 7 5 2 2 6 30 31 60 61 90 91 1 30 31 60 0 9 1 6 91 package ou t line, 1 20 le a d l q f p 18 . 0x18 . 0x1 . 7 m m lq m 120 r ev * *
document number: 002 - 08541 rev.*c page 112 of 117 mb9b510r s eries package type package code qfp 100 pqh100 0 02 - 15156 ** d i mensi o n s s ymb o l m i n . n o m . max. a 3 . 3 5 a 1 0. 0 5 0. 4 5 b 0 . 2 7 0 . 3 2 0 . 3 7 c 0 . 1 1 0 . 2 3 d 2 3 . 9 0 b sc d 1 2 0 . 0 0 b sc e 0 .6 5 bsc e e1 l 0 . 7 3 0 . 8 8 1 . 0 3 l 1 1 . 9 5 r ef l 2 0.2 5 bs c 1 7 . 9 0 b sc 1 4 . 0 0 b sc 0 8 l 2 0 3 1 10 0 e b d1 d 5 7 4 e e 1 3 6 4 5 7 0 . 2 0 c a - b d 7 5 2 0 . 1 3 c a - b d 8 0 . 4 0 c a - b d 3 2 s e a t i n g p l an e b s e cti o n a - a ' c 9 s i d e vie w t o p vie w a a ' 0 . 1 0 c 1 0 d e t a il a 3 1 5 0 5 1 8 0 8 1 1 3 0 10 0 3 1 5 0 0 8 1 5 8 1 b o tt o m vie w package ou t line, 100 lea d q fp 20 . 00x14.00x3 . 35 mm p q h 100 r ev * *
document number: 002 - 08541 rev.*c page 113 of 117 mb9b510r s eries package type package code fbga 112 lbc112 0 02 - 13225 ** n i s t h e n u m b e r o f p o p u l a t e d s o l d e r b a l l p o s i t i o n s f o r m a trix w hen t here i s an even number of s o l d e r ba ll s i n t h e o u t e r r o w , w hen t here i s an o dd number of s o l d e r ba ll s i n t h e o u t e r r o w , d e f i n e t h e positio n of t h e c e n t e r s o ld e r b a ll in t h e o u t e r r o w . " s d " and " se " are measured w i th r espe c t to d a t u m s a a nd b a nd s y m b o l " m e " i s t h e b a l l m a t r i x s i z e i n t h e " e " d i r e c t io n . s y m b o l " m d " i s t h e b a l l m a t r i x s i z e i n t h e " d " d i r e c t io n . "e" represents the sol d e r ba ll g r i d p i t ch . di m e n s i on " b " i s m e a s u r e d a t t h e m a x i m u m b a l l di a m e t e r in a so l d er bal l posi t i o n des i gna t i o n per jep 9 5 , sect i o n 3 , spp-020 . " + " i nd i cates the the o ret i cal c e n t e r of d ep o p u l a t e d s o l d e r a 1 c o r n e r t o b e i d e n t i f i e d b y c h amf e r, la s e r or i n k m a r k 8 . 7 . 6 . no t es : 5 . 4 . 3 . 2 . 1 . a l l di m e n s i on s a r e i n m i l l i m e t e r s . s d b e e e d m e n 0 . 3 5 0 . 0 0 0 . 8 0 bs c 0 . 8 0 bs c 0 . 4 5 11 2 1 1 0 . 5 5 d i m e n s io n s d1 m d e 1 e d a a 1 s y m b o l 0 . 2 5 m i n . - 8 . 0 0 bs c 8 . 0 0 bs c 1 1 1 0 . 0 0 bs c 1 0 . 0 0 bs c n o m . - 1 . 4 5 0 . 4 5 m ax . s e 0 . 0 0 0 . 3 5 m e t a l i z e d m a r k , i n d e n t a t i o n o r o t h e r m e a n s. " s d " = e d / 2 a n d " s e " = e e / 2 . plane parallel t o d a t u m c . " s d " or " s e " = 0 . siz e md x m e . b a ll s . a 0 . 20 c 2 x b 0 . 20 c 2 x i n d e x ma rk pin a 1 c o rne r 7 1 2 3 4 5 6 7 8 9 1 0 1 1 a b c d e f g h j k l 11 2 x b 0 . 08 c a b 5 6 6 s i d e vie w 0 . 10 c c d e t a il a b o tt o m vie w t o p vie w d e t a i l a 10 . 00x10 . 00 x1.45 mm l b c 112 r ev * * package ou t line, 11 2 ball f b g a
document number: 002 - 08541 rev.*c page 114 of 117 mb9b510r s eries 15. major changes spansion publication number: ds706 - 00025 page section change results revision 1.0 - - initial release revision 2.0 6 ? ? ? ? max: 10000 2000 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
document number: 002 - 08541 rev.*c page 115 of 117 mb9b510r s eries page section change results 76 ? electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main and usb pll (4 - 2) operating conditions of main pll added main pll clock frequency added usb clock frequency added the figure of main pll connection and usb pll connec tion 77 ? electrical characteristics 4. ac characteristics (6) power - on reset timing added time until releasing power - on reset changed the figure of timing 79 - 81 ? electrical characteristics 4. ac characteristics (7) external bus timing modified data o utput time 89 - 96 ? electrical characteristics 4. ac characteristics (8) csio/uart timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 103 ? electrical characteristics 5. 12bit a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage modified stage transition time to operation permission modified the minimum value of reference voltage 110 ? electrical characteristics 7. low - voltage detection characteristics (2) interrupt of low - voltage detection modified lvd stabilization wait time 111 ? electrical characteristics 9. workflash memory write/erase characteristics (1) write / erase time modified sector erase time modified half word(16 - bit) write time 112 - 11 5 ? electrical characteristics 9. return time from low - power consumption mode added return time from low - power consumption mode 116 ? ordering information change to full part number 117 - 12 0 ? package dimensions deleted fpt - 100p - m20 and fpt - 120p - m21 note: please see document history about later revised information.
document number: 002 - 08541 rev.*c page 11 6 of 117 mb9b510r s eries document history document title: mb9b510r series 32 - bit arm? cortex? - m3 fm3 microcontroller document number: 002 - 0 8541 revision ecn orig. of change submission date description of change ** - toyo 03/31/2015 migrated to cypress and assigned document number 002 - 08 541 . no change to document contents or format. *a 5175344 toyo 03/ 1 7 /2016 changed package code as below. fpt - 100p - m23 to lqi100 - 02 fpt - 120p - m37 to lqm120 - 02 fpt - 100p - m36 to pqh100 bga - 112p - m04 to lbc112 modified from usb function to usb device. p.19 modified i/o circuit type of md0 p.40 added the note of jtag pins. p.52 modified x1a of block diagram. p.7 0 modified max value of pll macro oscillation clock frequency to 144mhz. p.11 0 - 11 3 changed package dimensions. *b 5314949 toyo 06/ 16 /2016 p.109 modified part number. * c 5666809 yska 03 / 2 1 /201 7 modified rtc description in features, real - time clock(rtc) changed starting count value from 01 to 00. deleted second , or day of the week in the interrupt function ( page 3 ) updated 12.4.7 power - on reset timing. changed parameter from power supply rising time(t vccr )[ms] to power ramp rate(dv/dt)[mv/us] and added some comments ( pag e 71 ) updated packag e code as follows ( page 9 - 1 3 , 63 , 109 ) lqi100 - 02 - > lqi100 , lqm120 - 02 - > lqm120 updated 14. package dimensions ( page 110 - 113 ) modified typo in 13. ordering information ( page 109 ) added the baud rate spec in 12.4.10 csio/uart timing.( page 82 , 84 , 86 , 88 )
document number: 002 - 08541 rev.*c march 21, 2017 page 117 of 117 mb9b510r s eries sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless/rf cypress.com/wireless psoc? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | co mp onents technical support cypress.com/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? 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